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arch-arm: CPTR.FPEN controlling SVE enablement

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CheckSveEnabled shouldn't check for .ZEN only.
SVE instructions require Advanced SIMD to be supported as
well (CPTR.FPEN) with the caveat of ZEN check having priority
over the FPEN.

Change-Id: Ia1b5f7df3e25e7ffcad472542cb973635f62637b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28768
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-05-01 14:33:25 +01:00
parent 5aff442c76
commit 0b7e0199fb
1 changed files with 17 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
src/arch/arm/insts/static_inst.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2014, 2016-2019 ARM Limited
* Copyright (c) 2010-2014, 2016-2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -987,20 +987,33 @@ Fault
ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
{
const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
if ((el == EL0 && cpacr.zen != 0x3) ||
(el == EL1 && !(cpacr.zen & 0x1)))
return sveAccessTrap(EL1);
// Check if access disabled in CPACR_EL1
if (el <= EL1 && !ELIsInHost(tc, el)) {
if ((el == EL0 && cpacr.zen == 0x1) ||
(!(cpacr.zen & 0x1)))
return sveAccessTrap(EL1);
if ((el == EL0 && cpacr.fpen == 0x1) ||
(!(cpacr.fpen & 0x1)))
return advSIMDFPAccessTrap64(EL1);
}
// Check if access disabled in CPTR_EL2
if (ArmSystem::haveVirtualization(tc) && el <= EL2) {
CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL2);
if (cptr_en_check.tz)
return sveAccessTrap(EL2);
if (cptr_en_check.tfp)
return advSIMDFPAccessTrap64(EL2);
}
// Check if access disabled in CPTR_EL3
if (ArmSystem::haveSecurity(tc)) {
CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
if (!cptr_en_check.ez)
return sveAccessTrap(EL3);
if (cptr_en_check.tfp)
return advSIMDFPAccessTrap64(EL3);
}
return NoFault;