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arch-arm: Decode SEVL instruction for A32 and T32 IS

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The instruction had been defined but it was not used for AArch32

Change-Id: I2bb106e98647eaa1f4c71fffb541e76ac1688674
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28450
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-04-28 18:12:20 +01:00
parent 003c08418f
commit dcd5ca6402
2 changed files with 6 additions and 6 deletions
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5
src/arch/arm/isa/formats/branch.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2010,2012-2013,2017-2018 ARM Limited
// Copyright (c) 2010,2012-2013,2017-2018, 2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -187,8 +187,7 @@ def format Thumb32BranchesAndMiscCtrl() {{
case 0x4:
return new SevInst(machInst);
case 0x5:
return new WarnUnimplemented(
"sevl", machInst);
return new SevlInst(machInst);
}
break;
case 0x1:

7
src/arch/arm/isa/formats/data.isa
View File

@@ -1,4 +1,4 @@
// Copyright (c) 2010,2017-2018 ARM Limited
// Copyright (c) 2010,2017-2018, 2020 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1136,8 +1136,7 @@ def format ArmMisc() {{
case 0x4:
return new SevInst(machInst);
case 0x5:
return new WarnUnimplemented(
"sevl", machInst);
return new SevlInst(machInst);
case 0x10:
return new WarnUnimplemented(
"esb", machInst);
@@ -1283,6 +1282,8 @@ def format Thumb16Misc() {{
return new WfiInst(machInst);
case 0x4:
return new SevInst(machInst);
case 0x5:
return new SevlInst(machInst);
default:
return new WarnUnimplemented("unallocated_hint", machInst);
}