Commit Graph

12383 Commits

Author SHA1 Message Date
Gabe Black
3815ad14d7 arch-x86: Fix how MediaOps sets the size of its operands.
Because MediaOps have two sizes, one for sources and one for
destinations, it does not have a single dataSize member to set the size
of its operands. This was difficult to correct at the time, so a
dataSize member was created which was fixed at 0, and the instructions
themselves would use srcSize and destSize internally to do the actual
computation.

That causes problems when tracing, since the printReg function needs to
know what size to use to print some registers properly, specifically
integer registers.

To now fix that problem, some SFINAE constructors have been added which
will either pass through a dataSize member if one exists, or pass
through a pointer to the instruction itself so that operand index
selector class can pick out the member that makes sense for it (destSize
for DestOp, srcSize for Src1Op and Src2Op).

Change-Id: I6b8259a5ab27f809b81453bcf987cc6d1be4811a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49203
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2021-08-14 05:41:54 +00:00
Gabe Black
a759336a08 arch-arm: Fix style in utility.hh.
Change-Id: I66262e63695680f5638ef057be05274445ba38ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49144
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-08-14 00:35:07 +00:00
Gabe Black
29b20c9742 arch-x86: Stop printing a source operand for the monitor instruction.
Like CPUID, all operands for this instruction are implicit and are not
written out when putting it into assembly. Stop printing a source
operand when generating disassembly in gem5.

Change-Id: I95898afdd9101ad393b3aace99536db602752a64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49225
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2021-08-14 00:31:43 +00:00
Gabe Black
4ee5461300 arch-x86: Stop printing a source register for CPUID.
When disassembling the CPUID instruction, we were (for some reason)
printing a source register after the mneomic. The registers CPUID uses
are fixed, and it has no operands when written in assembly.

Change-Id: I5aee7f7a93cb84977cfe1fe387c5184aa740bc0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49224
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2021-08-14 00:31:23 +00:00
Gabe Black
6903547957 cpu-o3: Fix minor style issue in rename_map.hh.
Change-Id: I670e504320b41e38666dab6eb7a83e4a39bc3b00
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49146
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-12 22:01:30 +00:00
Gabe Black
7ffa9f8597 cpu: Simplify or eliminate set${type}Result methods for o3 and checker.
These methods are all identical now. The O3 versions can all be
consolidated into a single method. For the checker CPU, they can
actually be eliminated entirely, and the result queue's "emplace()"
method can be used to add items using less text than just calling the
original helper method.

Change-Id: Ifaeb3beeea257c8bbf951ee1dd8d2d5fd8bb3964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49128
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 20:24:54 +00:00
Gabe Black
91f7486482 cpu: Use std::variant to simplify InstResult.
std::variant is a similar to (and also modestly superior to)
MultiResult. Use it instead to simplify InstResult.

Change-Id: I22338f5e89814c6d13538129757158126013a414
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49127
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 20:24:54 +00:00
Gabe Black
7f540a333d x86: Fix disassembly of syscall instructions.
These *used* to have a source register which was the syscall number.
That was not an actual property of the instruction, it was a property of
the syscall mechanism in Linux which had leaked into the implementation
of the instructions themselves.

That was corrected by removing that source register and letting the
syscall handling layer figure out which system call to invoke.

Unfortunately the SyscallInst format wasn't also updated, and when
printing the disassembly for those instructions, it would try to print
that source register. That instruction doesn't bother to set up a source
operand array since it doesn't actually have any, so that ended up
accessing random memory.

Change-Id: I20890ad69605983305a13f414ca59a5fa35d4d06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49183
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 20:23:35 +00:00
Giacomo Travaglini
0a31476e1c arch-arm: Replace std::tie with C++17 structured binding
Change-Id: I856b60e91a0c8089ccc3560bdf9024b42206e170
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49084
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 08:20:34 +00:00
Gabe Black
1a4b6fbfe9 cpu: Get rid of double in InstResult::MultiResult.
Change-Id: Ib02b0e270e0a4fdfa036c0a271ff9c3ce2a98342
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 04:48:02 +00:00
Gabe Black
d5aeb809a7 cpu: Stop treating VecElem as its own case in InstResult.
Since this is now a RegVal, we can treat it as a Scalar result.

Change-Id: I0afd7815c1ebf20b50ce27a00b27bb408d2a32ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49125
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 04:48:02 +00:00
Gabe Black
9b1abd4d83 cpu: Use RegVal for VecElems instead of TheISA::VecElem.
If VecElem is a basic type, which is a reasonable assumption, it can be
contained in a RegVal. We still need to use the TheISA::VecElem type to
extract it from an actual vector, but then it can be passed around as a
RegVal.

Change-Id: I4dc470e7cc369499ce3686dd291eb3d93ca0819a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49124
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 04:48:02 +00:00
Gabe Black
b7c1c9561b cpu: Fix style in the checker CPU class.
Change-Id: Ief2d716b515ab38aaa202be49ef144f2c04f532e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49129
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 23:22:01 +00:00
Gabe Black
27c186f436 cpu: Fix style in inst_res.hh.
Change-Id: Ifc6d980f5dc0cec8b6ac58e4fb390ed49e3e1a39
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49123
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 23:21:46 +00:00
Bobby R. Bruce
d8da636bbb tests: Fix ExcludeInterleavingRanges test for .fast comp
Change-Id: Ie3ebfc0caa52f11649f479066022734ac82e6d1b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49065
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 22:40:56 +00:00
Gabe Black
f183942ab8 cpu: Rename RegClassInfo to RegClass.
Change-Id: I0456462d5d306fc93a1fe160e45ff6b1b49f3c25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49103
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 20:04:51 +00:00
Giacomo Travaglini
4da35850fb python: Provide a repoPath helper function
The function will return the absolute path of the gem5 repo
hosting the m5 library.
One of the use of this helper is to effectively refer/import
gem5 modules from EXTRAS repositories.

If I wanted to import the Ruby module from configs/ruby I could
do that with:

from m5.util import addToPath, repoPath

configs_path = os.path.join(repoPath(), configs)
addToPath(configs_path)

from ruby import Ruby

This isn't an out of tree scripts utility only: most of our configs are
currently relying on doing relative backward imports and could be ported
to use the repoPath utility:

addToPath(../..) is quite a common pattern

This makes the dependencies difficult to read/track and a bit fragile
as it all relies on the relative position between modules.

Change-Id: I26f6ef34b44f20903cc1b6248330b6156378f40b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49083
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-09 08:42:52 +00:00
Gabe Black
967c076256 cpu: Fix style in src/cpu/o3/cpu.hh.
Change-Id: I08802e184dfc0c9b4d96bc3ddf07af3a3a7f4e81
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49108
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-08-07 15:15:57 +00:00
Gabe Black
b7aebc1220 scons: Further simplify the_gpu_isa.hh.
Turn the "namespace" function into a simple variable. Also, since the
only thing defined in the file is a macro, we can drop the compiler
guards and use that macro as its own compiler guard.

Change-Id: I1e8559fc7add61105b2990f76226714ba282581d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48967
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-07 03:12:56 +00:00
Gabe Black
774f801589 scons: Remove cruft from the_gpu_isa.hh.
Some values in the_gpu_isa.hh were simply copy/pasted from the_isa.hh,
and were not used at all in the code. This change removes them, leaving
only the definition of the TheGpuISA namespace.

Change-Id: I0d66ae84d78e990088eb8099c678b9cf1cc42748
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48966
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-07 03:12:56 +00:00
Gabe Black
64168fd4ea scons: Turn the ISA and GPU ISA lists into construction variables.
Change-Id: I4135709f5bceee959b5178a4700656aa782b1d6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48965
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-08-07 03:12:56 +00:00
Gabe Black
a764139066 scons: Keep the list of all CPU models in a construction variable.
This relaxes ordering around CPU model declaration.

Change-Id: Ie5f8da1903a883bd4d98800dfbef7fd913021f77
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48964
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-08-07 03:12:56 +00:00
Gabe Black
2f053f1bc5 scons: Use a loop to build binary flavors.
Track structured data related to different binary flavors (opt, debug,
etc), using a class instead of various lists, etc. Also use a loop to
set up SCons environments to build these binaries instead of a spelled
out loop.

Change-Id: Ie35a914ab79342190e4cdc27a945a0fecd54a476
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48130
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-08-06 15:59:44 +00:00
Gabe Black
c8123df754 arch-gcn3: Fix initAtomicAccess.
This function used makeAtomicOpFunctor to create a unique_ptr which
pointed to an AtomicOpFunctor *, which it immediately extracted with
.get(). Then since the temporary unique_ptr went out of scope, it
deleted the AtomicOpFunctor which it just returned a pointer to.

Instead, that function should create a local unique_ptr to pass
ownership of the object off to. It will still be cleaned up when it
goes out of scope, but not before it's done being used.

Change-Id: I74a0bcbb719a78a3e9ec8cb2ea5aa15120da0456
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49023
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Kyle Roarty <kyleroarty1716@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 14:05:30 +00:00
Gabe Black
6811158b28 scons: Use sets instead of lists to track needed target environments.
This simple change intrinsically collapses away duplicates.

Change-Id: I697c21897a81c47cbf540caa49806413dce80dba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48129
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 10:50:06 +00:00
Gabe Black
9278d7eda4 scons: Remove the unused env.Label assignment in makeEnv.
Change-Id: I33fe01bb0381061528c450bc5e8312b52882615e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48128
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 10:49:59 +00:00
Gabe Black
1a8a3864cd scons: Use Dir().Dir() and not os.path to extend CPPPATH.
Since we're already working with Dir nodes, they can figure out
appending to a path themselves without using os.path.join.

Change-Id: Ib46946d7ec181dbbf443f957f23196eb0fd7f6b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48127
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 10:49:52 +00:00
Gabe Black
1c7f63c84a scons: Use the os.path prefix when using components of that module.
That makes it obvious where the methods involved are coming from. Also
some of the imported names weren't being used.

Change-Id: I6ec75eef1e5ea9eae51e7df675e477dccb351bd1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48126
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:42:20 +00:00
Gabe Black
0eab559913 scons: Delete the comparison operators from SourceFile.
These are apparently not used and can be deleted.

Change-Id: I201d565d2e0207e0f43e94bbbb43ec03c2b695ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48125
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:42:07 +00:00
Gabe Black
a74fe97ac9 scons: Eliminate the SourceFile.basename property.
This value is used in only two places, and can be calculated in place to
avoid complexity.

Change-Id: I1e59b92521250b3f5a3e2cba599236ededf1761d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48124
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:56 +00:00
Gabe Black
b159756d1c scons: Replace the SourceFile.filename property with attribute.
The SourceFile.filename property dynamically calculated the str()
conversion of self.tnode. Since self.tnode shouldn't be changed, it
doesn't seem useful to calculate that value over and over, especially
since it adds some extra indirection and magic to something that's
really pretty simple.

Change-Id: Ia0e1e8f4b0c019a026a08b5c2730d93c66de8190
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48123
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:44 +00:00
Gabe Black
14f2bfe389 scons: Replace the extname property with os.path.splitext().
This is almost exactly the same, except it leaves the "." on the
extension, and returns an empty string instead of None if there is no
extension.

Change-Id: Idb540771007f9f7ca8aafdb09512eb1219010237
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48122
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-08-06 04:41:28 +00:00
Gabe Black
fbe5ed97c0 scons: Get rid of the unused "dirname" property of SourceFile.
Change-Id: I7c52f866542057b9f11ba96434f9c6f93ff0ea46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48121
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:15 +00:00
Gabe Black
a5e2ef1429 scons: Make all Executables strip-able, and de-special case .fast.
The build for .fast was set up to produce a stripped executable, and the
unstripped executable was instead named .fast.unstripped. I think the
assumption that a stripped executable is faster than an unstripped
executable is flawed, since the parts of the binary that are removed,
debug symbols, are not loaded into memory anyway, so while the program
is executing it shouldn't be any different or take up any additional
memory. This also made .fast a special case compared to the other build
types, like .opt, .debug, etc.

Instead, this change makes .fast unstripped like all the other binaries,
and also makes it possible to request a stripped version of *any* binary
the build can produce with a .stripped suffix.

Change-Id: I2de82e0951d9f41c30594f32fba50acdd14ed69c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48120
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-06 04:41:15 +00:00
Gabe Black
c142629ccc arch,cpu: Rename RegClass to RegClassType.
This type is really an index which selects a RegClass, not a RegClass
itself.

A follow on change will rename RegClassInfo to RegClass.

Change-Id: I2c1b1d4105bd11b58680053b484d4c1aa1055a9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45229
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 19:05:32 +00:00
Jan Vrany
db9e64a570 base: handle initial communication with GDB in attach()
When remote GDB attaches to gem5, handle the initial communication
(`qSupported` and alike) right away instead of scheduling a `DataEvent`
and firing the simulation loop in hope that GDB will be quick enough to
send initial packets before instructions are dispatched.

This requires attach() to be always called at instruction boundary
to make it safe to interact with the rest of gem5.

When `--wait-gdb` is used, connect() is called from workflow startup,
therefore on an instruction boundary and therefore needs not special
handling.

To handle case the GDB connects while simulation is already running,
we arrange (new) assynchronous IncommingConnectionEvent on listening
socket that, when there's a new connection being made, *only* schedules
*synchronous* ConnectEvent that handles the rest, *including* calling
an accept() on listening socket. This way it is safe to process commands
in attach().

In order to make the code more systematic and easier to understands,
detach() is also made to be called only synchronously (that is, at
intruction boundary). Asynchronous events and event handlers are
prefixed with "incoming".

This seems to fix the race described in 44612 [1]

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/44612

Change-Id: I33b2922ba017205acabd51b6a8be3e6fb2d6409a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48182
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:43:20 +00:00
Jan Vrany
6ed6f9c807 base: Extract GDB command processing into separate function
Change-Id: I1f090285f92752d6907044b9ee6ade1869a2cb9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48181
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:43:20 +00:00
Giacomo Travaglini
79b57bbfb8 arch-arm: Add a shared L2 TLB to the default ArmMMU
JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I542c287a99c8b277afb4cd939c09521798dcf2f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48150
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
fb0929b5f9 arch-arm: Provide support for a multilevel-TLB in the ArmMMU
This is an initial implementation. It adapts the current MMU code
to account for extra levels of TLBs but it is still missing the
configurability we are looking for (to select the associativity
of the TLB and the replacement policy as an example)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I938ec38183337cd0e839bf3e3cd03594126128cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48149
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
395c6d4fa3 arch-arm: Explicitly implement I/DTLBI Ops in TLB
At the moment the ITLBI and DTLBI operations where implicitly
implemented as generic TLBIs

e.g:

* DTLBIASID, ITLBIASID = TLBIASID

This was possible as a single TLB was either an instruction TLB
or a data TLB and no generic/shared TLB option was available.
In other words, an ITLBI Op to an ITB was invalidating all entries
as we were sure the ITB was not containing data entries.

With shared TLBs, this doesn't hold true and we need to explicitly
implement I/DTLBIs

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I39a4add7674f6008dacaedfd1fd90560d264048e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48148
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
a23f39bc19 arch-arm: Distinguish Instruction from Data TLB entries
As we are going to support I+D (shared) TLBs we need to tag a TLB entry
as a data or instruction entry, so that I-TLBI and D-TLBI do not
over-invalidate entries

(The patch is also fixing the coding style of the TLB insertion
methods in the Table Walker)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I3d5880175fe6eda1b2f0edcbd0ea6a146d3c7a39
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48147
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
242d0d467a arch: Implement operator& for TypeTLB
Change-Id: I05af52ba5e0ef84510ca3f4c27d8f9cd55e07d90
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48463
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:26:33 +00:00
Daecheol You
8e00f8e582 mem-ruby: Atomic transaction support for CHI protocol
Ruby assumes protocols use directory controllers as memory interface.
Thus, recvAtomic() uses the machine type of directory when it calls
mapAddressToMachine(). However, it doesn't work for CHI since
CHI does not use directory controllers as memory controller interface.
Therefore, the code was modified to check which controller type is used
for memory interface between MachineType_Directory and
MachineType_Memory, which is used for CHI.

Change-Id: If35a06a8a3772ce5e5b994df05c9d94c7770c90d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48403
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 00:29:34 +00:00
Gabe Black
91e24ba776 misc: Replace THE_ISA macro with IS_NULL_ISA.
Now all occurances of the THE_ISA macro which were being used to check
for anything other than the NULL_ISA have been eliminated. We still need
to be able to check whether the current ISA is the null ISA, but we
don't want to let any preprocessor checks back in which are based on
what the current ISA is.

This change removes the THE_ISA macro, and replaces it with IS_NULL_ISA
which evaluates to 1 if the ISA is null, and 0 if it isn't.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: Iec146b40d8cab846dae03e15191390f754f2b71b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48709
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 21:04:22 +00:00
Gabe Black
b71029f02b cpu-minor: Use the RegClassInfo::regName method instead of THE_ISA.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I43b31897ed3a9e77c6d2908ac4a04f705a0f74f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48708
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 21:04:22 +00:00
Gabe Black
1e26e8f9a4 arm: Make the misc reg class return the name of misc regs.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: Ic2c8576b079c68f28b48006dd90515b1a5c68ed9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48707
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 21:04:22 +00:00
Giacomo Travaglini
1d600cd599 python: Expose the AddrRange exclude to the python world
Change-Id: I9cb1bf66d4e9390c8d3c4403afec9f896d19c162
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48904
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 09:18:40 +00:00
Giacomo Travaglini
19f2fd376b base: Add an exclude method to the AddrRange class
This will allow us to define a list of ranges provided an exclude
pattern, which is handy when a fragmented memory map is present

Change-Id: Ib3d76ef178355585d80e9e600b7c60e66efa01c1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48903
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 09:18:40 +00:00
Gabe Black
661611a8f6 cpu: Add a mechanism which lets a reg class name its members.
This can be used to get the "pretty" name for a given register index
within a register class, and can be specialized per ISA, or even per ISA
object.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I7b290db73c7d04e0f61293ae82fc92ca5b4fe692
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48706
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 06:07:22 +00:00
Gabe Black
f15032fbb2 cpu: Use the newly promoted uReset in the minor CPU.
Rather than use an #if THE_ISA check to see if the CPU can use the
microPC accessirs, this change uses the newly promoted/exposed uReset
for the same purpose.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1060

Change-Id: I4ac931624a2c8e2bbcd5189a05d9ec174bd03d4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48705
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-04 05:23:43 +00:00