Commit Graph

15448 Commits

Author SHA1 Message Date
Giacomo Travaglini
2e26b4a474 ext: Remove sandbox module from testlib
The sandbox module is providing a sandbox environment for
a specific TestCase via the multiprocessing package.

This isolation/complexity is not strictly needed as testlib is already
forking a new process via subprocess. As it is now, a TestRunner will
generate:

TestRunner -> multiprocessing.Process -> subprocess.Popen
(2 generated procs)

With this patch we are removing the intermediate layer

TestRunner -> subprocess.Popen
(1 generated proc)

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Icd5cadbe316653a9269ab098ec4c07f21b864ad3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30215
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
8c0d063e37 tests: log_call is not returning any value
JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I2713ddacc762d614e3992718ea234287d06c179a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30214
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Gabe Black
6b18ec642e mem: fixupAddr should not panic if it fails.
This function should just return false in that case, and its callers
should figure out what to do. Otherwise, when calling tryReadBlob in SE
mode, a failure to read the blob makes gem5 panic instead of just
returning false.

Change-Id: I74b9cb98f595c52300d683842ece68c6031d9b85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30376
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-18 03:58:48 +00:00
Gabe Black
187ba10c92 arch,cpu,sim: Eliminate the now empty kernel statistics classes.
This includes the base and ISA specific Kernel::Statistics classes, the
plumbing through ThreadContext to access them, and the switching
header file associated with them.

Change-Id: Ia511a59325b629aa9ccc0e695ddd47ff11916499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25149
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 19:54:41 +00:00
Gabe Black
44f787ae97 arch,kern,sim: Move the stats in Kernel::Statistics to Workload.
These are the stats in the base class, not in any derived classes. Only
Alpha has an additional stats. These were not really "kernel"
statistics, they were just applicable primarily in FS. They are
potentially applicable to any simulation, but will probably not be
incremented in SE simulations.

Also this merges these stats from being per thread to being per
workload, ie operating system instance. This is probably more relevant
since exactly what thread within a workload runs which particular
instruction is not very important/predictable, but the aggregate
behavior is. If necessary, this could be adjusted in the future to
split things back out again into stats per thread while keeping them
inside the single workload object.

Change-Id: I130e11a9022bdfcadcfb02c7995871503114cd53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25147
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 19:54:13 +00:00
Tony Gutierrez
9d51dec937 arch, gpu-compute: Remove HSAIL related files
Change-Id: Iefba0a38d62da7598bbfe3fe6ff46454d35144b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28410
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 02:53:47 +00:00
Gabe Black
d2beb1ffc8 mem: Use the new unbound port reporting mechanism in the mem ports.
There was an add-hoc check added to getAddrRanges, but the other methods
would just segfault if they tried to talk to their peers. This change
wraps all the calls in try blocks and catches the exception which the
peer will throw if it's the default and the port is not actually
connected to anything.

Change-Id: Ie46be0230f33f74305c599b251ca319a65ba008d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30296
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 20:15:12 +00:00
Nikos Nikoleris
35d9bf99a8 mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.

Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30055
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 16:13:43 +00:00
Gabe Black
d3024accaf sim: Add some helpers to catch and reporting using unbound ports.
If a port is unbound, trying to call its peer will likely cause a
segfault. Rather than check if a port is bound every time you go to use
it, we can instead bind to a default peer which just throws an exception
back to the caller. The caller can catch the exception and report the
error.

This change adds a common new class to throw as the exception, and also
a small utility function which reports the error and dies.

Change-Id: Ia58a2030922c73e2fd7d139822bce38d9b0f2171
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30295
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 02:35:41 +00:00
Gabe Black
5d80780f89 arm: Add missing overrides to the ARM interrupt object.
Change-Id: Idddc5267d5eb287a0895a1a2e1631ca9a2e789f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30294
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 23:31:15 +00:00
Tony Gutierrez
b8da9abba7 gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU model
Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29912
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 22:45:17 +00:00
Daniel R. Carvalho
b0eac7857a base: Delete deletePointer helpers
Now that the calls to deletePointer have been replaced by the use
of smart pointers, they can be safely removed.

Change-Id: I91d8b97f7ba3f64dd9948fd343cf0af969886598
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24251
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 19:52:54 +00:00
Nikos Nikoleris
6a4b69c4fd mem: Add a header latency parameter to the XBar
The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.

Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30054
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 12:57:52 +00:00
Giacomo Travaglini
ceb93d2182 tests: Use default None argument in makeArmSystem
JIRA: https://gem5.atlassian.net/browse/GEM5-387

Change-Id: I18b1ed360b2d285e4df19b896e692356ef6f8819
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30219
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
2020-06-14 19:26:40 +00:00
Gabe Black
d45c4b7523 scons: Fix how partial linking is disabled.
Setting disable_partial part way through the checks for various build
targets is incorrect and will affect targets based on the order they're
checked.

This change moves the check earlier, makes it consistent across all
builds whether fast is included or not, and stops passing it in as an
option to makeEnv since it now applies universally.

By disabling partial linking consistently, we avoid missing bugs where
only the "fast" version of gem5 doesn't build correctly because of the
multitude of g++ bugs having to do with combining LTO and partial
linking.

This also simplifies the logic in the SConscript by having fewer
independently moving parts.

Change-Id: Iff69f39868e948d3b9a5b11ea80bbfed19419b59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29303
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-06-12 08:48:14 +00:00
Gabe Black
1008b70f31 mem-ruby: Add a missing override.
Change-Id: I7651ca0f4658ddd49cfd13d9d5f7e430f416f41f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30254
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-12 06:23:23 +00:00
Gabe Black
260fc34c97 arch,cpu: Add a setThreadContext method to the ISA class.
Also remove ThreadContext pointer parameters to some of the methods in
the ISA classes.

Change-Id: I8e502b1857d299cb2e759a9734a1df4f65f31efe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29233
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-12 05:41:41 +00:00
Gabe Black
bd9fb89122 arch,cpu: Change setCPU to setThreadContext in Interrupts.
The ThreadContext can be used to access the cpu if needed, and is a
more representative interface to various pieces of state than the CPU
itself. Also convert some of the methods in Interupts to use the
locally stored ThreadContext pointer instead of taking one as an
argument. This makes calling those methods simpler and less error
prone.

Change-Id: I740bd99f92e54e052a618a4ae2927ea1c4ece193
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28988
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-11 23:42:54 +00:00
Kyle Roarty
432ecdfbdc sim-se: Ignore unimplemented system call
System call sched_setaffinity causes crashes when running programs
that use ROCm. Ignoring the system call allows for the programs
to run to completion.

Change-Id: I27c767ef81091789e228d47f2bb5f6fa18f11539
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30154
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-11 21:00:12 +00:00
Gabe Black
9757529064 sim: Delete an unused member in the System class.
This was supposed to be deleted as part of the change titled:
arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.

but it was left out of the checked in version somehow.

Change-Id: I0dbb0b4fa6ae29649a80d1cb883e48ad50116c31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30194
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-11 03:00:33 +00:00
Bobby R. Bruce
c1bf5469d8 misc: Reverted version information to "develop"
Change-Id: I6ee1bae48f2dd0d868dfbb428e93deeb9ee93083
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29833
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-10 20:46:52 +00:00
Gabe Black
0dfa59f0bb arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.
The System class has a few different arrays of values which each
correspond to a thread of execution based on their position. This
change collects them together into a single class to make managing them
easier and less error prone. It also collects methods for manipulating
those threads as an API for that class.

This class acts as a collection point for thread based state which the
System class can look into to get at all its state. It also acts as an
interface for interacting with threads for other classes. This forces
external consumers to use the API instead of accessing the individual
arrays which improves consistency.

Change-Id: Idc4575c5a0b56fe75f5c497809ad91c22bfe26cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25144
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 23:37:29 +00:00
Gabe Black
5da62e6331 arch,base,cpu,kerm,sim: Build a symbol table for object files.
Instead of calling into object files after the fact and asking them to
put symbols into a target symbol table, this change makes object files
fill in a symbol table themselves at construction. Then, that table can
be retrieved and used to fill in aggregate tables, masked, moved,
and/or filtered to have only one type of symbol binding.

This simplifies the symbol management API of the object file types
significantly, and makes it easier to deal with symbol tables alongside
binaries in the FS workload classes.

Change-Id: Ic9006ca432033d72589867c93d9c5f8a1d87f73c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24787
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 23:37:29 +00:00
Xianwei Zhang
7f4d6c8388 mem-ruby: Add codes for pure virtual functions for compilation
Change-Id: Ic34f9ccf10ec28d68eed236dc6246e2ae2ef1b89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28409
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2020-06-09 20:00:13 +00:00
Tuan Ta
adc9de4d61 mem-ruby: update memory interfaces to support GPU ISA
This patch deprecates HSA-based memory request types and adds new
types that can be used by real ISA instructions.

Change-Id: Ie107a69d8a35e9de0853f1407392ad01a8b3e930
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28408
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 20:00:13 +00:00
Gabe Black
18e435546c mem: Default the SE translating port proxy alloc method to NextPage.
This is what's used in 99% of cases, so it makes sense to make it the
default.

Change-Id: I51535b3387d1c1a0d1d89e77cfca10363388b472
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29399
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 10:02:26 +00:00
Bobby R. Bruce
b801b9ed04 misc: Merge hotfix v20.0.0.2 into develop
Change-Id: Ia0ed6bfb70e2ebcb22274569556d690e315702bd
2020-06-08 15:27:51 -07:00
Bobby R. Bruce
96fce47678 misc: Updated release notes and version number
Change-Id: Ib8583c23f47010222c08ff5aa9cffb842235c784
2020-06-08 15:21:35 -07:00
Matthew Poremba
bbb6a3fe8d mem-ruby: Allow MachineID to be unordered key
Define an std::hash function so that MachineID may be used as a key
type for unordered STL containers.

Change-Id: Ibc3bc78149c69683207d8967542fa6e8d545f75c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29652
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-08 16:39:21 +00:00
Giacomo Travaglini
7ce081d583 misc: Remove any reference to the ALPHA ISA
Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30015
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-08 09:00:55 +00:00
seanzw
e30ef9911f mem-ruby: Fix Prefetcher to RubyPrefetcher in StateMachine.
After renaming Prefetcher to RubyPrefetcher, the slicc generator
should be updated to correctly initialize the prefetcher with
the controller.

Change-Id: Ia12a4640c35aaedd70a4a14e5a10793b060ba924
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29974
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-05 22:14:12 +00:00
Tommaso Marinelli
872cb227fd mem-cache: prevent prefetcher from saturating the write buffer
When the write buffer is full, it still has space to store an additional
number of entries (reserve) equal to the number of MSHRs so that if any
of them requires a writeback this can be handled. Even if the slave port
is blocked, a prefetcher can generate new MSHR entries that may lead to
additional writebacks and eventually saturate the reserve space. This is
solved by checking if the cache is blocked for accesses before
prefetching data.

Change-Id: Iaad04dd6786a09eab7afae4a53d1b1299c341f33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29615
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-04 22:35:15 +00:00
Gabe Black
1d081f5054 systemc: Replace include of eventq_impl.hh with eventq.hh.
eventq_impl.hh has been merged back into eventq.hh, but that change
passed another change which started using eventq_impl.hh in systemc.

Change-Id: I2e9be5f993fe6a6712a121cd955b0c56a33c87e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30014
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-04 17:59:31 +00:00
Gabe Black
415abb3a3c sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
Having some methods (which are supposed to be inline) defined in another
file which is only included sometimes creates a lot of opportunities for
errors. They no longer need to be separate, so merge them together.

Change-Id: I5846e55f53f59b9c2081680a6441659265a765f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29409
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-04 01:54:19 +00:00
Gabe Black
d64173549b base,sim: Move DTRACE into base/debug.hh.
All other considerations aside, DTRACE probably fits best in trace.hh
where it is now, but unfortunately that creates an awkward dependence
between that file and eventq.hh and eventq_impl.hh. DTRACE only depends
on flags in the Debug namespace and a universal macro TRACING_ON, so
even though it won't be alongside the things it's most logically
associated with, it will be alongside all of its dependencies.

An alternative would be to re-implement DTRACE in eventq_impl.hh which
wouldn't be too big of a problem because it's so simple, but it's
cleaner and less error prone to still keep a single definition.

Because base/trace.hh includes base/debug.hh, any consumers expecting to
find DTRACE in base/trace.hh will still get that definition, even though
it's no longer direct.

Change-Id: I0dac83295891630686c3a8038eb54138cf40ab44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29411
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2020-06-03 22:32:45 +00:00
Gabe Black
89f2d5eb54 misc: Make many includes explicit.
A future change will adjust how some includes can be included
transitively. This change fixes up those files so that they include the
headers they need directly, instead of expecting to have them by
accident through other files.

Change-Id: I1f79aa11df2b46bb7018f39c964294c41db4fdac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29407
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-03 19:42:46 +00:00
Tiago Mück
8c47c0dd63 cpu-o3: fix IQ missing mem barriers
After commit e2a5063e5f some
memory references now tracked as barriers were not having
their completion properly notified to the MemDepUnit.

This patch fixes InstructionQueue and changes MemDepUnit's
completeBarrier to completeInst, which now should be called
for both memory references and barrier instructions.

Change-Id: I28b5f112b45778f6272e71bb3766b364c3d2e7db
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29654
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-02 18:39:14 +00:00
Bobby R. Bruce
43512da4b2 misc: Merge branch version update into develop 2020-06-02 00:20:23 -07:00
Bobby R. Bruce
332a9de33d misc: Updated release notes and version to v20.0.0.1 2020-06-02 00:16:28 -07:00
Bobby R. Bruce
5e3158d593 misc: Merge in 'hotfix-m5-tick-rounding-error' 2020-06-01 22:46:51 -07:00
Hoa Nguyen
4e484ca33e python: Fix m5's tick rounding mechanism
Partially reverts:
https://gem5-review.googlesource.com/c/public/gem5/+/29372 where the
`math.ceil` function was used to fix an issue where 0.5 was rounded to
zero in python3. This has the side effect of giving incorrect clock
frequences due to rounding errors. To demonstrate:

```
>>> import math
>>> 1e-9*1000000000000
1000.0000000000001
>>> int(math.ceil(1e-9*1000000000000))
1001
```

The solution to this problem is to use Python's `decimal` module to
round values.

Issue-on: https://gem5.atlassian.net/browse/GEM5-616
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: Ic76736ccb4b6b8c037103a34493aff7d9731d314
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29577
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-01 19:40:49 +00:00
adarshpatil
0a5ed3076a mem-ruby: Fix for Invalid transition in MOESI_CMP_directory
Send the correct sharer count from the memory directory to the requesting
L2 cache in data message reply.

Jira issue: https://gem5.atlassian.net/browse/GEM5-613

Change-Id: If76de630fd0001816e8836d9bf77961a94faaa7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29552
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-29 19:31:47 +00:00
Onur Kayiran
5587dd94f0 mem-ruby: Generate address with masking cacheline bits
makeLineAddress function uses m_block_size_bits to create
masked addresses. m_block_size_bits is used to specify
cache, directory, and memory controller interleaving,
and it can be larger than the cache line size.
To generate addresses that can align with the cache line
rather than the interleaving granularity, a version of
makeLineAddress is created to specify bits that need to
be masked.

Change-Id: I06deec4949da7fa46f1d6f7575334f18ee61c786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28135
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Onur Kayıran <onur.kayiran@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-05-28 23:07:08 +00:00
Onur Kayiran
dee6b07006 configs: Specify cache, dir, and mem cntrl interleaving
This changeset allows setting a variable for interleaving.
That value is used together with the number of directories to
calculate numa_high_bit, which is in turn used to set up
cache, directory, and memory controller interleaving.
A similar approach is used to set xor_low_bit, and calculate
xor_high_bit for address hashing.

Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 23:07:08 +00:00
Tuan Ta
e071f60011 mem-ruby: add function to check for stalled msgs of addr
This patch allows a cache controller to check if there
is any stalled message of a specific address in the
stall_map of an input message buffer.

Change-Id: Id2f9bb98a9201a562f2a8cc371e9bb896ac836af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28133
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 23:07:08 +00:00
Tuan Ta
524c22041d mem-ruby: add slicc stm to defer enqueueing a message
This patch enables cache controllers to make response
messages in advance, store them in a per-address saved
map in an output message buffer and enqueue them altogether
in the future. This patch introduces new slicc statement
called defer_enqueueing. This patch would help simplify
the logic of state machines that deal with coalesing
multiple requests from different requestors.

Change-Id: I566d4004498b367764238bb251260483c5a1a5e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28132
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-05-28 23:07:08 +00:00
Bobby R. Bruce
90332c45b5 Merge branch 'release-staging-v20.0.0.0' into develop 2020-05-28 15:52:09 -07:00
Giacomo Travaglini
b1b8af0443 system: Remove CNTFRQ_EL0 write from arm64 boot
We don't need this anymore since this is initialized at gem5
construction.

JIRA: https://gem5.atlassian.net/browse/GEM5-611

Change-Id: I42a3d53a4defba498a23d9a7c192dfff5852c1c7
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29613
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-28 22:44:12 +00:00
Giacomo Travaglini
3dd3c1e893 dev-arm: Make CNTFRQ a GenericTimer parameter
This register should be in theory initialized by the highest
priviledged software. We do this in gem5 to avoid KVM
complications (the gem5 firmware won't run at highest EL)

JIRA: https://gem5.atlassian.net/browse/GEM5-611

Change-Id: I62d368105af48584f2fe9671de7c70b484b40c12
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29612
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-05-28 22:44:12 +00:00
Bobby R. Bruce
e53de444f6 misc: Merge branch 'release-staging-v20.0.0.0' into develop 2020-05-28 01:04:16 -07:00