mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and therefore the latency it adds would overlap with them. This patch fixes the MemDelay to properly account for them. Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30055 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018 ARM Limited
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* Copyright (c) 2018, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@@ -87,7 +87,12 @@ MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
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bool
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MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
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{
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const Tick when = curTick() + parent.delayResp(pkt);
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// technically the packet only reaches us after the header delay,
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// and typically we also need to deserialise any payload
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const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
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pkt->headerDelay = pkt->payloadDelay = 0;
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const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
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parent.slavePort.schedTimingResp(pkt, when);
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@@ -136,7 +141,13 @@ MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
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bool
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MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
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{
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const Tick when = curTick() + parent.delayReq(pkt);
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// technically the packet only reaches us after the header
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// delay, and typically we also need to deserialise any
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// payload
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Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
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pkt->headerDelay = pkt->payloadDelay = 0;
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const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
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parent.masterPort.schedTimingReq(pkt, when);
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