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mem-ruby: Fix for Invalid transition in MOESI_CMP_directory

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Send the correct sharer count from the memory directory to the requesting
L2 cache in data message reply.

Jira issue: https://gem5.atlassian.net/browse/GEM5-613

Change-Id: If76de630fd0001816e8836d9bf77961a94faaa7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29552
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
adarshpatil
2020-05-27 21:43:08 +01:00
committed by Adarsh Patil
parent 5587dd94f0
commit 0a5ed3076a
1 changed files with 5 additions and 1 deletions
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6
src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
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@@ -469,7 +469,11 @@ machine(MachineType:Directory, "Directory protocol")
out_msg.Destination.add(in_msg.OriginalRequestorMachId);
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Dirty := false; // By definition, the block is now clean
out_msg.Acks := in_msg.Acks;
if (getDirectoryEntry(in_msg.addr).Sharers.isElement(in_msg.OriginalRequestorMachId) == true) {
out_msg.Acks := (getDirectoryEntry(in_msg.addr).Sharers.count()) - 1;
} else {
out_msg.Acks := getDirectoryEntry(in_msg.addr).Sharers.count();
}
if (in_msg.ReadX) {
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
} else {