derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm: Add missing overrides to the ARM interrupt object.

Browse Source 
Change-Id: Idddc5267d5eb287a0895a1a2e1631ca9a2e789f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30294
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-06-12 21:09:46 -07:00
parent b8da9abba7
commit 5d80780f89
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/arch/arm/interrupts.hh
View File

@@ -77,7 +77,7 @@ class Interrupts : public BaseInterrupts
void
post(int int_num, int index)
post(int int_num, int index) override
{
DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
@@ -92,7 +92,7 @@ class Interrupts : public BaseInterrupts
}
void
clear(int int_num, int index)
clear(int int_num, int index) override
{
DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
@@ -107,7 +107,7 @@ class Interrupts : public BaseInterrupts
}
void
clearAll()
clearAll() override
{
DPRINTF(Interrupt, "Interrupts all cleared\n");
intStatus = 0;
@@ -123,7 +123,7 @@ class Interrupts : public BaseInterrupts
bool takeInt(InterruptTypes int_type) const;
bool
checkInterrupts() const
checkInterrupts() const override
{
HCR hcr = tc->readMiscReg(MISCREG_HCR);