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arch,cpu: Change setCPU to setThreadContext in Interrupts.

Browse Source 
The ThreadContext can be used to access the cpu if needed, and is a
more representative interface to various pieces of state than the CPU
itself. Also convert some of the methods in Interupts to use the
locally stored ThreadContext pointer instead of taking one as an
argument. This makes calling those methods simpler and less error
prone.

Change-Id: I740bd99f92e54e052a618a4ae2927ea1c4ece193
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28988
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-05-12 13:09:23 -07:00
parent 432ecdfbdc
commit bd9fb89122
19 changed files with 113 additions and 166 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/interrupts.cc
View File

@@ -46,7 +46,7 @@ ArmInterruptsParams::create()
}
bool
ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const
ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
{
// Table G1-17~19 of ARM V8 ARM
InterruptMask mask;

40
src/arch/arm/interrupts.hh
View File

@@ -57,19 +57,11 @@ namespace ArmISA
class Interrupts : public BaseInterrupts
{
private:
BaseCPU * cpu;
bool interrupts[NumInterruptTypes];
uint64_t intStatus;
public:
void
setCPU(BaseCPU * _cpu)
{
cpu = _cpu;
}
typedef ArmInterruptsParams Params;
const Params *
@@ -78,7 +70,7 @@ class Interrupts : public BaseInterrupts
return dynamic_cast<const Params *>(_params);
}
Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
Interrupts(Params * p) : BaseInterrupts(p)
{
clearAll();
}
@@ -128,10 +120,10 @@ class Interrupts : public BaseInterrupts
INT_MASK_P // pending
};
bool takeInt(ThreadContext *tc, InterruptTypes int_type) const;
bool takeInt(InterruptTypes int_type) const;
bool
checkInterrupts(ThreadContext *tc) const
checkInterrupts() const
{
HCR hcr = tc->readMiscReg(MISCREG_HCR);
@@ -150,9 +142,9 @@ class Interrupts : public BaseInterrupts
(hcr.va && allowVAbort)) )
return false;
bool take_irq = takeInt(tc, INT_IRQ);
bool take_fiq = takeInt(tc, INT_FIQ);
bool take_ea = takeInt(tc, INT_ABT);
bool take_irq = takeInt(INT_IRQ);
bool take_fiq = takeInt(INT_FIQ);
bool take_ea = takeInt(INT_ABT);
return ((interrupts[INT_IRQ] && take_irq) ||
(interrupts[INT_FIQ] && take_fiq) ||
@@ -220,9 +212,9 @@ class Interrupts : public BaseInterrupts
}
Fault
getInterrupt(ThreadContext *tc)
getInterrupt() override
{
assert(checkInterrupts(tc));
assert(checkInterrupts());
HCR hcr = tc->readMiscReg(MISCREG_HCR);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@@ -236,9 +228,9 @@ class Interrupts : public BaseInterrupts
bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
bool take_irq = takeInt(tc, INT_IRQ);
bool take_fiq = takeInt(tc, INT_FIQ);
bool take_ea = takeInt(tc, INT_ABT);
bool take_irq = takeInt(INT_IRQ);
bool take_fiq = takeInt(INT_FIQ);
bool take_ea = takeInt(INT_ABT);
if (interrupts[INT_IRQ] && take_irq)
return std::make_shared<Interrupt>();
@@ -262,21 +254,17 @@ class Interrupts : public BaseInterrupts
panic("intStatus and interrupts not in sync\n");
}
void
updateIntrInfo(ThreadContext *tc)
{
; // nothing to do
}
void updateIntrInfo() override {} // nothing to do
void
serialize(CheckpointOut &cp) const
serialize(CheckpointOut &cp) const override
{
SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
SERIALIZE_SCALAR(intStatus);
}
void
unserialize(CheckpointIn &cp)
unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
UNSERIALIZE_SCALAR(intStatus);

2
src/arch/arm/isa/insts/misc.isa
View File

@@ -721,7 +721,7 @@ let {{
SevMailbox = 0;
PseudoInst::quiesceSkip(tc);
} else if (tc->getCpuPtr()->getInterruptController(
tc->threadId())->checkInterrupts(tc)) {
tc->threadId())->checkInterrupts()) {
PseudoInst::quiesceSkip(tc);
} else {
fault = trapWFx(tc, cpsr, scr, true);

10
src/arch/generic/interrupts.hh
View File

@@ -37,14 +37,14 @@ class BaseCPU;
class BaseInterrupts : public SimObject
{
protected:
BaseCPU *cpu;
ThreadContext *tc = nullptr;
public:
typedef BaseInterruptsParams Params;
BaseInterrupts(Params *p) : SimObject(p) {}
virtual void setCPU(BaseCPU * newCPU) = 0;
virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
const Params *
params() const
@@ -59,16 +59,16 @@ class BaseInterrupts : public SimObject
/*
* Return whether there are any interrupts waiting to be recognized.
*/
virtual bool checkInterrupts(ThreadContext *tc) const = 0;
virtual bool checkInterrupts() const = 0;
/*
* Return an interrupt to process. This should return an interrupt exactly
* when checkInterrupts returns true.
*/
virtual Fault getInterrupt(ThreadContext *tc) = 0;
virtual Fault getInterrupt() = 0;
/*
* Update interrupt related state after an interrupt has been processed.
*/
virtual void updateIntrInfo(ThreadContext *tc) = 0;
virtual void updateIntrInfo() = 0;
/*
* Old functions needed for compatability but which will be phased out

40
src/arch/mips/interrupts.cc
View File

@@ -39,20 +39,22 @@ namespace MipsISA
{
static inline uint8_t
getCauseIP(ThreadContext *tc) {
getCauseIP(ThreadContext *tc)
{
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
return cause.ip;
}
static inline void
setCauseIP(ThreadContext *tc, uint8_t val) {
setCauseIP(ThreadContext *tc, uint8_t val)
{
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
cause.ip = val;
tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
}
void
Interrupts::post(int int_num, ThreadContext* tc)
Interrupts::post(int int_num)
{
DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
if (int_num < 0 || int_num >= NumInterruptLevels)
@@ -70,7 +72,7 @@ Interrupts::post(int int_num, int index)
}
void
Interrupts::clear(int int_num, ThreadContext* tc)
Interrupts::clear(int int_num)
{
DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
if (int_num < 0 || int_num >= NumInterruptLevels)
@@ -88,24 +90,18 @@ Interrupts::clear(int int_num, int index)
}
void
Interrupts::clearAll(ThreadContext *tc)
Interrupts::clearAll()
{
DPRINTF(Interrupt, "Interrupts all cleared\n");
uint8_t intstatus = 0;
setCauseIP(tc, intstatus);
}
void
Interrupts::clearAll()
{
fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
}
bool
Interrupts::checkInterrupts(ThreadContext *tc) const
Interrupts::checkInterrupts() const
{
if (!interruptsPending(tc))
if (!interruptsPending())
return false;
//Check if there are any outstanding interrupts
@@ -126,9 +122,9 @@ Interrupts::checkInterrupts(ThreadContext *tc) const
}
Fault
Interrupts::getInterrupt(ThreadContext * tc)
Interrupts::getInterrupt()
{
assert(checkInterrupts(tc));
assert(checkInterrupts());
StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
@@ -139,7 +135,7 @@ Interrupts::getInterrupt(ThreadContext * tc)
}
bool
Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
Interrupts::onCpuTimerInterrupt() const
{
RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
@@ -148,19 +144,15 @@ Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
return false;
}
void
Interrupts::updateIntrInfo(ThreadContext *tc)
{
//Nothing needs to be done.
}
void Interrupts::updateIntrInfo() {} // Nothing needs to be done.
bool
Interrupts::interruptsPending(ThreadContext *tc) const
Interrupts::interruptsPending() const
{
//if there is a on cpu timer interrupt (i.e. Compare == Count)
//update CauseIP before proceeding to interrupt
if (onCpuTimerInterrupt(tc)) {
DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
if (onCpuTimerInterrupt()) {
DPRINTF(Interrupt, "Interrupts OnCpuTimerInterrupt() == true\n");
//determine timer interrupt IP #
IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
uint8_t intStatus = getCauseIP(tc);

25
src/arch/mips/interrupts.hh
View File

@@ -55,11 +55,7 @@ class Interrupts : public BaseInterrupts
return dynamic_cast<const Params *>(_params);
}
Interrupts(Params * p) : BaseInterrupts(p)
{
}
void setCPU(BaseCPU *_cpu) override {}
Interrupts(Params * p) : BaseInterrupts(p) {}
// post(int int_num, int index) is responsible
// for posting an interrupt. It sets a bit
@@ -67,7 +63,7 @@ class Interrupts : public BaseInterrupts
// MIPS register Cause is updated by updateIntrInfo
// which is called by checkInterrupts
//
void post(int int_num, ThreadContext *tc);
void post(int int_num);
void post(int int_num, int index) override;
// clear(int int_num, int index) is responsible
@@ -76,7 +72,7 @@ class Interrupts : public BaseInterrupts
// MIPS register Cause is updated by updateIntrInfo
// which is called by checkInterrupts
//
void clear(int int_num, ThreadContext* tc);
void clear(int int_num);
void clear(int int_num, int index) override;
// clearAll() is responsible
@@ -85,25 +81,24 @@ class Interrupts : public BaseInterrupts
// MIPS register Cause is updated by updateIntrInfo
// which is called by checkInterrupts
//
void clearAll(ThreadContext *tc);
void clearAll() override;
// getInterrupt(ThreadContext * tc) checks if an interrupt
// getInterrupt() checks if an interrupt
// should be returned. It ands the interrupt mask and
// and interrupt pending bits to see if one exists. It
// also makes sure interrupts are enabled (IE) and
// that ERL and ERX are not set
//
Fault getInterrupt(ThreadContext *tc) override;
Fault getInterrupt() override;
// updateIntrInfo(ThreadContext *tc) const syncs the
// updateIntrInfo() const syncs the
// MIPS cause register with the instatus variable. instatus
// is essentially a copy of the MIPS cause[IP7:IP0]
//
void updateIntrInfo(ThreadContext *tc) override;
bool interruptsPending(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
bool checkInterrupts(ThreadContext *tc) const override;
void updateIntrInfo() override;
bool interruptsPending() const;
bool onCpuTimerInterrupt() const;
bool checkInterrupts() const override;
void
serialize(CheckpointOut &cp) const override

20
src/arch/power/interrupts.hh
View File

@@ -40,9 +40,6 @@ namespace PowerISA {
class Interrupts : public BaseInterrupts
{
private:
BaseCPU * cpu;
public:
typedef PowerInterruptsParams Params;
@@ -52,14 +49,7 @@ class Interrupts : public BaseInterrupts
return dynamic_cast<const Params *>(_params);
}
Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
{}
void
setCPU(BaseCPU * _cpu)
{
cpu = _cpu;
}
Interrupts(Params *p) : BaseInterrupts(p) {}
void
post(int int_num, int index)
@@ -80,20 +70,20 @@ class Interrupts : public BaseInterrupts
}
bool
checkInterrupts(ThreadContext *tc) const
checkInterrupts() const
{
panic("Interrupts::checkInterrupts not implemented.\n");
}
Fault
getInterrupt(ThreadContext *tc)
getInterrupt()
{
assert(checkInterrupts(tc));
assert(checkInterrupts());
panic("Interrupts::getInterrupt not implemented.\n");
}
void
updateIntrInfo(ThreadContext *tc)
updateIntrInfo()
{
panic("Interrupts::updateIntrInfo not implemented.\n");
}

19
src/arch/riscv/interrupts.hh
View File

@@ -53,7 +53,6 @@ namespace RiscvISA {
class Interrupts : public BaseInterrupts
{
private:
BaseCPU * cpu;
std::bitset<NumInterruptTypes> ip;
std::bitset<NumInterruptTypes> ie;
@@ -66,12 +65,10 @@ class Interrupts : public BaseInterrupts
return dynamic_cast<const Params *>(_params);
}
Interrupts(Params * p) : BaseInterrupts(p), cpu(nullptr), ip(0), ie(0) {}
void setCPU(BaseCPU * _cpu) { cpu = _cpu; }
Interrupts(Params * p) : BaseInterrupts(p), ip(0), ie(0) {}
std::bitset<NumInterruptTypes>
globalMask(ThreadContext *tc) const
globalMask() const
{
INTERRUPT mask = 0;
STATUS status = tc->readMiscReg(MISCREG_STATUS);
@@ -85,23 +82,23 @@ class Interrupts : public BaseInterrupts
}
bool checkInterrupt(int num) const { return ip[num] && ie[num]; }
bool checkInterrupts(ThreadContext *tc) const
bool checkInterrupts() const
{
return (ip & ie & globalMask(tc)).any();
return (ip & ie & globalMask()).any();
}
Fault
getInterrupt(ThreadContext *tc)
getInterrupt()
{
assert(checkInterrupts(tc));
std::bitset<NumInterruptTypes> mask = globalMask(tc);
assert(checkInterrupts());
std::bitset<NumInterruptTypes> mask = globalMask();
for (int c = 0; c < NumInterruptTypes; c++)
if (checkInterrupt(c) && mask[c])
return std::make_shared<InterruptFault>(c);
return NoFault;
}
void updateIntrInfo(ThreadContext *tc) {}
void updateIntrInfo() {}
void
post(int int_num, int index)

18
src/arch/sparc/interrupts.hh
View File

@@ -56,19 +56,11 @@ enum InterruptTypes
class Interrupts : public BaseInterrupts
{
private:
BaseCPU * cpu;
uint64_t interrupts[NumInterruptTypes];
uint64_t intStatus;
public:
void
setCPU(BaseCPU * _cpu) override
{
cpu = _cpu;
}
typedef SparcInterruptsParams Params;
const Params *
@@ -77,7 +69,7 @@ class Interrupts : public BaseInterrupts
return dynamic_cast<const Params *>(_params);
}
Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
Interrupts(Params * p) : BaseInterrupts(p)
{
clearAll();
}
@@ -129,7 +121,7 @@ class Interrupts : public BaseInterrupts
}
bool
checkInterrupts(ThreadContext *tc) const override
checkInterrupts() const override
{
if (!intStatus)
return false;
@@ -187,9 +179,9 @@ class Interrupts : public BaseInterrupts
}
Fault
getInterrupt(ThreadContext *tc) override
getInterrupt() override
{
assert(checkInterrupts(tc));
assert(checkInterrupts());
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
@@ -243,7 +235,7 @@ class Interrupts : public BaseInterrupts
return NoFault;
}
void updateIntrInfo(ThreadContext *tc) override {}
void updateIntrInfo() override {}
uint64_t
get_vec(int int_num)

34
src/arch/x86/interrupts.cc
View File

@@ -266,20 +266,20 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector,
}
}
if (FullSystem)
cpu->wakeup(0);
tc->getCpuPtr()->wakeup(0);
}
void
X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
X86ISA::Interrupts::setThreadContext(ThreadContext *_tc)
{
assert(newCPU);
if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
panic("Local APICs can't be moved between CPUs"
" with different IDs.\n");
}
cpu = newCPU;
initialApicId = cpu->cpuId();
assert(_tc);
panic_if(tc != NULL && tc->cpuId() != _tc->cpuId(),
"Local APICs can't be moved between CPUs with different IDs.");
BaseInterrupts::setThreadContext(_tc);
initialApicId = tc->cpuId();
regs[APIC_ID] = (initialApicId << 24);
pioAddr = x86LocalAPICAddress(initialApicId, 0);
}
@@ -343,7 +343,7 @@ X86ISA::Interrupts::completeIPI(PacketPtr pkt)
AddrRangeList
X86ISA::Interrupts::getAddrRanges() const
{
assert(cpu);
assert(tc);
AddrRangeList ranges;
ranges.push_back(RangeSize(pioAddr, PageBytes));
return ranges;
@@ -593,7 +593,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
}
X86ISA::Interrupts::Interrupts(Params * p)
X86ISA::Interrupts::Interrupts(Params *p)
: BaseInterrupts(p), sys(p->system), clockDomain(*p->clk_domain),
apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
pendingSmi(false), smiVector(0),
@@ -602,7 +602,7 @@ X86ISA::Interrupts::Interrupts(Params * p)
pendingInit(false), initVector(0),
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0), cpu(NULL),
pendingIPIs(0),
intSlavePort(name() + ".int_slave", this, this),
intMasterPort(name() + ".int_master", this, this, p->int_latency),
pioPort(this), pioDelay(p->pio_latency)
@@ -618,7 +618,7 @@ X86ISA::Interrupts::Interrupts(Params * p)
bool
X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
X86ISA::Interrupts::checkInterrupts() const
{
RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
if (pendingUnmaskableInt) {
@@ -648,9 +648,9 @@ X86ISA::Interrupts::checkInterruptsRaw() const
}
Fault
X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
X86ISA::Interrupts::getInterrupt()
{
assert(checkInterrupts(tc));
assert(checkInterrupts());
// These are all probably fairly uncommon, so we'll make them easier to
// check for.
if (pendingUnmaskableInt) {
@@ -682,9 +682,9 @@ X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
}
void
X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
X86ISA::Interrupts::updateIntrInfo()
{
assert(checkInterrupts(tc));
assert(checkInterrupts());
if (pendingUnmaskableInt) {
if (pendingSmi) {
DPRINTF(LocalApic, "SMI sent to core.\n");

13
src/arch/x86/interrupts.hh
View File

@@ -66,7 +66,8 @@ class BaseCPU;
int divideFromConf(uint32_t conf);
namespace X86ISA {
namespace X86ISA
{
ApicRegIndex decodeAddr(Addr paddr);
@@ -170,8 +171,6 @@ class Interrupts : public BaseInterrupts
void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
BaseCPU *cpu;
int initialApicId;
// Ports for interrupts.
@@ -193,7 +192,7 @@ class Interrupts : public BaseInterrupts
*/
typedef X86LocalApicParams Params;
void setCPU(BaseCPU * newCPU) override;
void setThreadContext(ThreadContext *_tc) override;
const Params *
params() const
@@ -261,7 +260,7 @@ class Interrupts : public BaseInterrupts
* Functions for retrieving interrupts for the CPU to handle.
*/
bool checkInterrupts(ThreadContext *tc) const override;
bool checkInterrupts() const override;
/**
* Check if there are pending interrupts without ignoring the
* interrupts disabled flag.
@@ -275,8 +274,8 @@ class Interrupts : public BaseInterrupts
* @return true there are unmaskable interrupts pending.
*/
bool hasPendingUnmaskable() const { return pendingUnmaskableInt; }
Fault getInterrupt(ThreadContext *tc) override;
void updateIntrInfo(ThreadContext *tc) override;
Fault getInterrupt() override;
void updateIntrInfo() override;
/*
* Serialization.

20
src/cpu/base.cc
View File

@@ -170,17 +170,6 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
}
}
// The interrupts should always be present unless this CPU is
// switched in later or in case it is a checker CPU
if (!params()->switched_out && !is_checker) {
fatal_if(interrupts.size() != numThreads,
"CPU %s has %i interrupt controllers, but is expecting one "
"per thread (%i)\n",
name(), interrupts.size(), numThreads);
for (ThreadID tid = 0; tid < numThreads; tid++)
interrupts[tid]->setCPU(this);
}
if (FullSystem) {
if (params()->profile)
profileEvent = new EventFunctionWrapper(
@@ -432,6 +421,11 @@ BaseCPU::registerThreadContexts()
{
assert(system->multiThread || numThreads == 1);
fatal_if(interrupts.size() != numThreads,
"CPU %s has %i interrupt controllers, but is expecting one "
"per thread (%i)\n",
name(), interrupts.size(), numThreads);
ThreadID size = threadContexts.size();
for (ThreadID tid = 0; tid < size; ++tid) {
ThreadContext *tc = threadContexts[tid];
@@ -444,6 +438,8 @@ BaseCPU::registerThreadContexts()
if (!FullSystem)
tc->getProcessPtr()->assignThreadContext(tc->contextId());
interrupts[tid]->setThreadContext(tc);
}
}
@@ -628,7 +624,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
interrupts = oldCPU->interrupts;
for (ThreadID tid = 0; tid < numThreads; tid++) {
interrupts[tid]->setCPU(this);
interrupts[tid]->setThreadContext(threadContexts[tid]);
}
oldCPU->interrupts.clear();

4
src/cpu/base.hh
View File

@@ -252,9 +252,9 @@ class BaseCPU : public ClockedObject
}
bool
checkInterrupts(ThreadContext *tc) const
checkInterrupts(ThreadID tid) const
{
return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc);
return FullSystem && interrupts[tid]->checkInterrupts();
}
void processProfileEvent();

2
src/cpu/intr_control.cc
View File

@@ -72,7 +72,7 @@ IntrControl::havePosted(int cpu_id) const
{
DPRINTF(IntrControl, "Check pending interrupts for CPU %d\n", cpu_id);
auto *tc = sys->threads[cpu_id];
return tc->getCpuPtr()->checkInterrupts(tc);
return tc->getCpuPtr()->checkInterrupts(tc->threadId());
}
IntrControl *

6
src/cpu/kvm/x86_cpu.cc
View File

@@ -1141,8 +1141,8 @@ X86KvmCPU::deliverInterrupts()
// they are getInterrupt() and updateIntrInfo() are called
// atomically.
EventQueue::ScopedMigration migrate(interrupts[0]->eventQueue());
fault = interrupts[0]->getInterrupt(tc);
interrupts[0]->updateIntrInfo(tc);
fault = interrupts[0]->getInterrupt();
interrupts[0]->updateIntrInfo();
}
X86Interrupt *x86int(dynamic_cast<X86Interrupt *>(fault.get()));
@@ -1200,7 +1200,7 @@ X86KvmCPU::kvmRun(Tick ticks)
// the thread context and check if there are /really/
// interrupts that should be delivered now.
syncThreadContext();
if (lapic->checkInterrupts(tc)) {
if (lapic->checkInterrupts()) {
DPRINTF(KvmInt,
"M5 has pending interrupts, delivering interrupt.\n");

8
src/cpu/minor/execute.cc
View File

@@ -409,7 +409,7 @@ Execute::handleMemResponse(MinorDynInstPtr inst,
bool
Execute::isInterrupted(ThreadID thread_id) const
{
return cpu.checkInterrupts(cpu.getContext(thread_id));
return cpu.checkInterrupts(thread_id);
}
bool
@@ -418,13 +418,11 @@ Execute::takeInterrupt(ThreadID thread_id, BranchData &branch)
DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n",
cpu.getContext(thread_id)->pcState());
Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt
(cpu.getContext(thread_id));
Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt();
if (interrupt != NoFault) {
/* The interrupt *must* set pcState */
cpu.getInterruptController(thread_id)->updateIntrInfo
(cpu.getContext(thread_id));
cpu.getInterruptController(thread_id)->updateIntrInfo();
interrupt->invoke(cpu.getContext(thread_id));
assert(!lsq.accessesInFlight());

6
src/cpu/o3/commit_impl.hh
View File

@@ -733,7 +733,7 @@ void
DefaultCommit<Impl>::handleInterrupt()
{
// Verify that we still have an interrupt to handle
if (!cpu->checkInterrupts(cpu->tcBase(0))) {
if (!cpu->checkInterrupts(0)) {
DPRINTF(Commit, "Pending interrupt is cleared by master before "
"it got handled. Restart fetching from the orig path.\n");
toIEW->commitInfo[0].clearInterrupt = true;
@@ -813,7 +813,7 @@ DefaultCommit<Impl>::commit()
{
if (FullSystem) {
// Check if we have a interrupt and get read to handle it
if (cpu->checkInterrupts(cpu->tcBase(0)))
if (cpu->checkInterrupts(0))
propagateInterrupt();
}
@@ -1125,7 +1125,7 @@ DefaultCommit<Impl>::commitInsts()
//
// If we don't do this, we might end up in a live lock situation
if (!interrupt && avoidQuiesceLiveLock &&
onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
onInstBoundary && cpu->checkInterrupts(0))
squashAfter(tid, head_inst);
} else {
DPRINTF(Commit, "Unable to commit head instruction PC:%s "

4
src/cpu/o3/cpu.cc
View File

@@ -891,7 +891,7 @@ Fault
FullO3CPU<Impl>::getInterrupts()
{
// Check if there are any outstanding interrupts
return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
return this->interrupts[0]->getInterrupt();
}
template <class Impl>
@@ -905,7 +905,7 @@ FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
// @todo: Allow other threads to handle interrupts.
assert(interrupt != NoFault);
this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
this->interrupts[0]->updateIntrInfo();
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
this->trap(interrupt, 0, nullptr);

6
src/cpu/simple/base.cc
View File

@@ -439,12 +439,12 @@ BaseSimpleCPU::checkForInterrupts()
SimpleThread* thread = t_info.thread;
ThreadContext* tc = thread->getTC();
if (checkInterrupts(tc)) {
Fault interrupt = interrupts[curThread]->getInterrupt(tc);
if (checkInterrupts(curThread)) {
Fault interrupt = interrupts[curThread]->getInterrupt();
if (interrupt != NoFault) {
t_info.fetchOffset = 0;
interrupts[curThread]->updateIntrInfo(tc);
interrupts[curThread]->updateIntrInfo();
interrupt->invoke(tc);
thread->decoder.reset();
}