mem-ruby: update memory interfaces to support GPU ISA
This patch deprecates HSA-based memory request types and adds new types that can be used by real ISA instructions. Change-Id: Ie107a69d8a35e9de0853f1407392ad01a8b3e930 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28408 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tuan Ta
committed by
Anthony Gutierrez
Anthony Gutierrez
parent
18e435546c
commit
adc9de4d61
@@ -181,6 +181,10 @@ MemCmd::commandInfo[] =
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{ 0, InvalidCmd, "Deprecated_MessageResp" },
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/* MemFenceReq -- for synchronization requests */
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{SET2(IsRequest, NeedsResponse), MemFenceResp, "MemFenceReq"},
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/* MemSyncReq */
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{SET2(IsRequest, NeedsResponse), MemSyncResp, "MemSyncReq"},
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/* MemSyncResp */
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{SET1(IsResponse), InvalidCmd, "MemSyncResp"},
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/* MemFenceResp -- for synchronization responses */
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{SET1(IsResponse), InvalidCmd, "MemFenceResp"},
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/* Cache Clean Request -- Update with the latest data all existing
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@@ -110,6 +110,8 @@ class MemCmd
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SwapResp,
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// MessageReq and MessageResp are deprecated.
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MemFenceReq = SwapResp + 3,
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MemSyncReq, // memory synchronization request (e.g., cache invalidate)
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MemSyncResp, // memory synchronization response
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MemFenceResp,
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CleanSharedReq,
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CleanSharedResp,
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@@ -110,7 +110,7 @@ class Request
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* STRICT_ORDER flag should be set if such reordering is
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* undesirable.
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*/
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UNCACHEABLE = 0x00000400,
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UNCACHEABLE = 0x00000400,
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/**
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* The request is required to be strictly ordered by <i>CPU
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* models</i> and is non-speculative.
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@@ -216,35 +216,30 @@ class Request
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};
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/** @} */
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typedef uint32_t MemSpaceConfigFlagsType;
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typedef ::Flags<MemSpaceConfigFlagsType> MemSpaceConfigFlags;
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typedef uint64_t CacheCoherenceFlagsType;
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typedef ::Flags<CacheCoherenceFlagsType> CacheCoherenceFlags;
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enum : MemSpaceConfigFlagsType {
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/** Has a synchronization scope been set? */
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SCOPE_VALID = 0x00000001,
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/** Access has Wavefront scope visibility */
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WAVEFRONT_SCOPE = 0x00000002,
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/** Access has Workgroup scope visibility */
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WORKGROUP_SCOPE = 0x00000004,
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/** Access has Device (e.g., GPU) scope visibility */
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DEVICE_SCOPE = 0x00000008,
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/** Access has System (e.g., CPU + GPU) scope visibility */
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SYSTEM_SCOPE = 0x00000010,
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/** Global Segment */
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GLOBAL_SEGMENT = 0x00000020,
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/** Group Segment */
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GROUP_SEGMENT = 0x00000040,
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/** Private Segment */
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PRIVATE_SEGMENT = 0x00000080,
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/** Kergarg Segment */
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KERNARG_SEGMENT = 0x00000100,
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/** Readonly Segment */
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READONLY_SEGMENT = 0x00000200,
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/** Spill Segment */
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SPILL_SEGMENT = 0x00000400,
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/** Arg Segment */
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ARG_SEGMENT = 0x00000800,
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/**
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* These bits are used to set the coherence policy
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* for the GPU and are encoded in the GCN3 instructions.
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* See the AMD GCN3 ISA Architecture Manual for more
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* details.
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*
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* SLC: System Level Coherent. Accesses are forced to miss in
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* the L2 cache and are coherent with system memory.
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*
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* GLC: Globally Coherent. Controls how reads and writes are
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* handled by the L1 cache. Global here referes to the
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* data being visible globally on the GPU (i.e., visible
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* to all WGs).
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*
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* For atomics, the GLC bit is used to distinguish between
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* between atomic return/no-return operations.
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*/
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enum : CacheCoherenceFlagsType {
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/** user-policy flags */
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SLC_BIT = 0x00000080,
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GLC_BIT = 0x00000100,
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};
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using LocalAccessor =
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@@ -305,8 +300,8 @@ class Request
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/** Flag structure for the request. */
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Flags _flags;
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/** Memory space configuraiton flag structure for the request. */
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MemSpaceConfigFlags _memSpaceConfigFlags;
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/** Flags that control how downstream cache system maintains coherence*/
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CacheCoherenceFlags _cacheCoherenceFlags;
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/** Private flags for field validity checking. */
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PrivateFlags privateFlags;
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@@ -394,7 +389,7 @@ class Request
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_byteEnable(other._byteEnable),
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_masterId(other._masterId),
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_flags(other._flags),
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_memSpaceConfigFlags(other._memSpaceConfigFlags),
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_cacheCoherenceFlags(other._cacheCoherenceFlags),
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privateFlags(other.privateFlags),
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_time(other._time),
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_taskId(other._taskId), _vaddr(other._vaddr),
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@@ -629,10 +624,11 @@ class Request
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}
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void
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setMemSpaceConfigFlags(MemSpaceConfigFlags extraFlags)
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setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
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{
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// TODO: do mem_sync_op requests have valid paddr/vaddr?
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assert(privateFlags.isSet(VALID_PADDR | VALID_VADDR));
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_memSpaceConfigFlags.set(extraFlags);
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_cacheCoherenceFlags.set(extraFlags);
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}
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/** Accessor function for vaddr.*/
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@@ -840,82 +836,10 @@ class Request
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* Accessor functions for the memory space configuration flags and used by
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* GPU ISAs such as the Heterogeneous System Architecture (HSA). Note that
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* these are for testing only; setting extraFlags should be done via
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* setMemSpaceConfigFlags().
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* setCacheCoherenceFlags().
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*/
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bool isScoped() const { return _memSpaceConfigFlags.isSet(SCOPE_VALID); }
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bool
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isWavefrontScope() const
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{
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assert(isScoped());
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return _memSpaceConfigFlags.isSet(WAVEFRONT_SCOPE);
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}
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bool
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isWorkgroupScope() const
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{
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assert(isScoped());
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return _memSpaceConfigFlags.isSet(WORKGROUP_SCOPE);
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}
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bool
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isDeviceScope() const
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{
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assert(isScoped());
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return _memSpaceConfigFlags.isSet(DEVICE_SCOPE);
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}
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bool
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isSystemScope() const
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{
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assert(isScoped());
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return _memSpaceConfigFlags.isSet(SYSTEM_SCOPE);
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}
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bool
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isGlobalSegment() const
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{
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return _memSpaceConfigFlags.isSet(GLOBAL_SEGMENT) ||
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(!isGroupSegment() && !isPrivateSegment() &&
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!isKernargSegment() && !isReadonlySegment() &&
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!isSpillSegment() && !isArgSegment());
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}
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bool
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isGroupSegment() const
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{
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return _memSpaceConfigFlags.isSet(GROUP_SEGMENT);
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}
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bool
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isPrivateSegment() const
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{
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return _memSpaceConfigFlags.isSet(PRIVATE_SEGMENT);
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}
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bool
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isKernargSegment() const
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{
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return _memSpaceConfigFlags.isSet(KERNARG_SEGMENT);
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}
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bool
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isReadonlySegment() const
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{
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return _memSpaceConfigFlags.isSet(READONLY_SEGMENT);
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}
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bool
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isSpillSegment() const
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{
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return _memSpaceConfigFlags.isSet(SPILL_SEGMENT);
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}
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bool
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isArgSegment() const
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{
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return _memSpaceConfigFlags.isSet(ARG_SEGMENT);
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}
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bool isSLC() const { return _cacheCoherenceFlags.isSet(SLC_BIT); }
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bool isGLC() const { return _cacheCoherenceFlags.isSet(GLC_BIT); }
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/**
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* Accessor functions to determine whether this request is part of
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@@ -58,16 +58,11 @@ class RubyRequest : public Message
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WriteMask m_writeMask;
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DataBlock m_WTData;
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int m_wfid;
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HSAScope m_scope;
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HSASegment m_segment;
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RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len,
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uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
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PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No,
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ContextID _proc_id = 100, ContextID _core_id = 99,
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HSAScope _scope = HSAScope_UNSPECIFIED,
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HSASegment _segment = HSASegment_GLOBAL)
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ContextID _proc_id = 100, ContextID _core_id = 99)
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: Message(curTime),
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m_PhysicalAddress(_paddr),
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m_Type(_type),
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@@ -77,9 +72,7 @@ class RubyRequest : public Message
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m_Prefetch(_pb),
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data(_data),
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m_pkt(_pkt),
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m_contextId(_core_id),
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m_scope(_scope),
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m_segment(_segment)
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m_contextId(_core_id)
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{
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m_LineAddress = makeLineAddress(m_PhysicalAddress);
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}
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@@ -89,9 +82,7 @@ class RubyRequest : public Message
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RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb,
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unsigned _proc_id, unsigned _core_id,
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int _wm_size, std::vector<bool> & _wm_mask,
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DataBlock & _Data,
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HSAScope _scope = HSAScope_UNSPECIFIED,
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HSASegment _segment = HSASegment_GLOBAL)
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DataBlock & _Data)
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: Message(curTime),
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m_PhysicalAddress(_paddr),
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m_Type(_type),
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@@ -104,9 +95,7 @@ class RubyRequest : public Message
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m_contextId(_core_id),
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m_writeMask(_wm_size,_wm_mask),
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m_WTData(_Data),
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m_wfid(_proc_id),
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m_scope(_scope),
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m_segment(_segment)
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m_wfid(_proc_id)
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{
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m_LineAddress = makeLineAddress(m_PhysicalAddress);
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}
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@@ -117,9 +106,7 @@ class RubyRequest : public Message
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unsigned _proc_id, unsigned _core_id,
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int _wm_size, std::vector<bool> & _wm_mask,
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DataBlock & _Data,
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std::vector< std::pair<int,AtomicOpFunctor*> > _atomicOps,
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HSAScope _scope = HSAScope_UNSPECIFIED,
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HSASegment _segment = HSASegment_GLOBAL)
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std::vector< std::pair<int,AtomicOpFunctor*> > _atomicOps)
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: Message(curTime),
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m_PhysicalAddress(_paddr),
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m_Type(_type),
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@@ -132,14 +119,11 @@ class RubyRequest : public Message
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m_contextId(_core_id),
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m_writeMask(_wm_size,_wm_mask,_atomicOps),
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m_WTData(_Data),
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m_wfid(_proc_id),
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m_scope(_scope),
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m_segment(_segment)
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m_wfid(_proc_id)
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{
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m_LineAddress = makeLineAddress(m_PhysicalAddress);
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}
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RubyRequest(Tick curTime) : Message(curTime) {}
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MsgPtr clone() const
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{ return std::shared_ptr<Message>(new RubyRequest(*this)); }
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