Commit Graph

17098 Commits

Author SHA1 Message Date
Bobby R. Bruce
1aea08ff81 python,tests: Update pyunit tests to run in TestLib
Previously the pyunit tests needed run in the gem5 root, this change
allows them to run as part of the quick TestLib tests (thereby having
them run as part of the presubmit checks). This runs all the TestLib
tests as a single test using the NULL gem5 binary.

`tests/run_pyunit.py` has been updated to only parse files with the
`pyunit` prefix in their filname. As such `pyunit/util/test_convert.py`
has been renamed `pyunit/util/pyunit_convert_check.py`. The word `test`
has been removed entirely as to not clash with the testlib tests as run
by `tests/main.py`.

Example usage:

```
./main.py run --uid SuiteUID:tests/pyunit/test_run.py:pyunit-tests-NULL-x86_64-opt
```

Discussed briefly in email thread:
https://www.mail-archive.com/gem5-dev@gem5.org/msg38563.html

Change-Id: Id566d44fcb5d8c599eb1a90bca56793158a201e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44625
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-27 18:31:58 +00:00
Matthew Poremba
f0e2c7cfc7 configs: Handle various DMA devices in GPU_VIPER
Viper is checking for the dma's type before making the port assignment.
In FullSystem mode the IDE device is a PortRef and does not have an
attribute 'type.' This handles the various types a bit better and
ensures that IDE device, the protocol tester, and upcoming DMA devices
related to FullSystem can be added.

Change-Id: I6879b25c6aabbbc22b0ee8dc9cbfec6399f70daa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44806
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-27 13:58:31 +00:00
Giacomo Travaglini
70abb2dcfd sim: Use memPools in SE mode only
memPools have been added by:

https://gem5-review.googlesource.com/c/public/gem5/+/42215

and are supposed to be used in SE mode only.
Current code is assuming there is at least one memory which is visible
to the OS/bootloader (conf_table_reported = True). This makes sense
in SE mode as it emulates the OS, but it shouldn't be enforced
in FS baremetal simulations

With this patch we are making sure memPools are used in SE mode
only.

Change-Id: Icebb7dafc18a6fdad0f9b16e5a988270bbebb9eb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44845
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-27 12:32:14 +00:00
Giacomo Travaglini
60f7618a0f configs: Remove unused argument from create_mem_intf
The number of memory controllers is not actually used by the
create_mem_intf function

Change-Id: I8663b38938de9b62b778679c1bc5c7c6e15a60da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42075
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-27 10:45:18 +00:00
Gabe Black
605399893c arch,base,cpu: Move some type aliases into base/types.hh.
The arch/generic/types.hh header includes some more complicated types
which in turn bring in more dependencies, adding baggage when other code
only needs the simple RegIndex or ElemIndex types. Also the RegVal type
alias is already in base/types.hh. It doesn't really make sense to have
RegVal in one header and RegIndex in another.

Change-Id: I1360652598b5fa59e0632b1ee0e0535ace2ba563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42966
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-27 02:19:11 +00:00
Matthew Poremba
4ef0bd03ab configs: Only add CPU sequencers to piobus
GPUCoalescers in FullSystem mode should not be connected to the piobus
since they reside on a completely different RubyPort. There is also no
concept of IO requests from GPU so any request attempting to use the
default port (pio) should fatal. Further, coalescers do not implement
the connectIOPorts function.

This avoids coalescers by checking is_cpu_sequencer, which I believe is
the purpose of that boolean.

Change-Id: I482dd631292ca20e3bcd856489376f9b38457200
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44805
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-26 22:09:54 +00:00
Gabe Black
f3b2d51baf arch-riscv: Pull non-public content out of arch/registers.hh.
Change-Id: If75ebddcaa677ccb76269a41f74f310298e2611d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41736
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-25 05:43:44 +00:00
Matthew Poremba
fd9addede1 configs: apu_se.py hotfix
Missed two optparse -> argparse changes. Square runs.

Change-Id: I3a652380e4c4202a376413602fa3698a28ff9206
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44825
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-24 21:43:20 +00:00
Kyle Roarty
529736a7ce gpu-compute, dev-hsa: Fix doorbell for gfx900
gfx9 changed the size of the doorbell, and what the write index
is when the doorbell is rang. --gfx-version flag is used to set
the doorbell size

Change-Id: I48e4e57dc1c80a08133b17cdf3f92533b541f7c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42220
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-24 15:54:15 +00:00
Kyle Roarty
ec6b325382 gpu-compute, dev-hsa: Remove HSADriver, HSADevice
HSADriver/HSADevice were primarily used with GPUCommandProcessor/
GPUComputeDriver. This change merges the classes together to
simplify the inheritance hierarchy, as well as removing any casting.

Change-Id: I670eb9b49a16c8aba17e13fd1d1287d0621c9f48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42219
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-24 15:54:15 +00:00
Michael LeBeane
d019912efa dev-hsa: Fix doorbell mmap for APU
Commit id ef44dc9a removed mmap-based doorbell allocation since dGPUs
use ioctl's instead.  However, APUs still need this to work correctly.
Add that logic back in as well as some new logic to distinguish doorbells
mmaps from other types. Also add some additional commentary regarding
Event page mmaps.

Change-Id: I8507ac85c8f07886d0fb4f95bde5e18a7790eab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42218
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-24 15:54:15 +00:00
Kyle Roarty
eb09361eef configs, gpu-compute: Add option to specify gfx version
Currently uses gfx801, gfx803, gfx900 for Carrizo, Fiji,
and Vega respectively

Change-Id: I62758914b6a60f16dd4f2141a23c0a9141a4e1a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42217
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-24 15:54:15 +00:00
Michael LeBeane
ad43083bb3 gpu-compute: Implement per-request MTYPEs
GPU MTYPE is currently set using a global config passed to the
PACoalescer.  This patch enables MTYPE to be set by the shader on a
per-request bases.  In real hardware, the MTYPE is extracted from a
GPUVM PTE during address translation.  However, our current simulator
only models x86 page tables which do not have the appropriate bits for
GPU MTYPES.  Rather than hacking non-x86 bits into our x86 page table
models, this patch instead keeps an interval tree of all pages that
request custom MTYPES in the driver itself.  This is currently
only used to map host pages to the GPU as uncacheable, but is easily
extensible to other MTYPES.

Change-Id: I7daab0ffae42084b9131a67c85cd0aa4bbbfc8d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42216
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-24 15:54:15 +00:00
Daniel R. Carvalho
dfa712f041 tests: Make the ISA-dependent tests run
dev/ has unit tests, but they are not run when
using the NULL ISA. The currently existing tests
are not ISA-specific, so the tests were set to
be run at an ARM environment.

As of now this is enough, but when ISA-specific
tests from ISAs other than ARM are added one will
need to change to cover them too.

Change-Id: I18df0141d415286325463afa759459b04ac8a92f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44367
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-24 15:26:53 +00:00
Matthew Poremba
4f7d15a70b configs: Update apu_se.py argparse support
There was a merge error caused by new options being added to this script
while all scripts were being converted from optparse. This fixes the
error.

This also removes the mostly unused setOption / getOption as you can
directly assign a value to an argument after parsing

Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba5f0fbf5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44785
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-23 20:52:03 +00:00
Gabe Black
f403edf6b4 base: Introduce versions of mul(Uns|S)igned which return two values.
This makes code which needs to call lots of different sized multiplications.

Change-Id: Id0d28be4c304214171840e7916c2e90ecfcd3840
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42360
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-04-23 04:55:13 +00:00
Gabe Black
a18241a6c1 base: Teach gem5 how to use 128 bit types for multiplication.
gcc provides __uint128_t and __int128_t types which represent 128 bit
wide unsigned and signed integers, respectively. We can detect that
extension and use it to perform wide multiplication which takes
advantage of the built in single multiply instruction on x86 hardware
without having to compute the value manually with 64 bit variables.

Since both gcc and clang should support this extension and the manual
version may not be exercised normally, this change also extends the
gtest for intmath so that it will explicitly run the manual versions of
these functions. On systems with the extension both versions will be
tested, and on other systems the manual version will be harmlessly
tested twice.

Change-Id: I32640679396584cd43bc91a3f7e649c6e6f94afa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42359
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-04-23 04:55:13 +00:00
Gabe Black
6f5668be86 base: Create wide multiply functions in intmath.hh.
These implementations are from the x86 multiply microops. When
multipying two integers of a certain width together, these functions
will produce two values of the same size which hold the upper and lower
part of the multiplication result.

The version which works for 32 bit values and smaller just takes
advantage of 64 bit multiplication using standard types. The 64 bit
version needs to do more work since there isn't a built in standard
facility for doing those sorts of multiplications.

Change-Id: If7b3d3aa174dd13aae6f383772cbc5291181de5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42358
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-23 04:55:13 +00:00
Gabe Black
d7d549408f base: Check the context ID when replacing a ThreadContext in GDB.
This says *which* thread context you're replacing. Right now it's
implied that you're replacing the only thread context, but once we
support having multiple threads in the same GDB endpoint, that will no
longer be implied.

Change-Id: I5a789d12bbe195e019d5ccd8a005b5a6f16b9299
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44610
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-04-22 22:30:51 +00:00
Gabe Black
14f2a031c6 arch-arm: Simplify the "mult" SIMD instructions with a BitUnion.
These instructions go through a lot of effort to extract bitfields, sign
extend them, and cast things to an appropriate type/size.

Instead, we can define a BitUnion which has the appropriate ranges of
bits predefined, and take advantage of the fact that every bitfield
returns its value as either a uint64_t if it's unsigned, or an int64_t
if it's signed.

Also, stop setting resTemp if it's not going to be used to set condition
codes or used as an intermediate in calculating the destination
registers.

Change-Id: Ia511aa74c823fad48080de4fbf77791c0cb3309d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42387
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 22:12:16 +00:00
Michael LeBeane
e4537dfbba sim: Add pool specific allocators to SE mode
The System object supports multiple memory pools but there is currently
no way to specify which pool to allocate from in SE mode.  This patch
adds a optional poolID argument to the allocation functions.

Change-Id: I1c732f28905f3b3875adee5f2b0d9abb39a6c5d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42215
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 20:01:33 +00:00
Gabe Black
3c3c2c3076 cpu: Simplify the RegId class a little.
Having const and non const reference accessors for the RegId index are
basically the same thing as just making the index value public but with
more complexity. Stop allowing updates through the accessor, and
simplify/fix the one location that was using that.

Also, there is no good reason to return an integer value by const
reference instead of returning it by value, since the value being passed
around (a pointer) is the same size, and just makes the value harder to
access.

Change-Id: I377ffc5878ef9bffa2ac53626a87c019a585ab1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42684
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 15:12:42 +00:00
Gabe Black
6f3c197742 cpu: Eliminate the isZeroReg() helper in RegId.
The isZeroReg() helper checked if the register was both an integer
register, and if it equaled TheISA::ZeroReg. This bakes in both the
assumption that any zero registers are integer (and that integer
registers are a thing), and also internalizes the plumbing which selects
what index is the zero register.

This change eliminates the isZeroReg helper and moves the logic inside
it into where it was called. In most cases, it was actually not
necessary to check if the register was integer since that was already
implied by context. This also brings the TheISA::ZeroReg constant out,
where it can be replaced by values plumbed in more generally than a
fixed, ISA specific constant.

Change-Id: I651762b6eb01fea83ec0b0076e8be9bf24b5b0da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42683
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 12:50:48 +00:00
Boris Shingarov
ee58010f0d sim: Trap into GDB instead of panicking on SEGV
When a segfault happens in the guest, report a SEGV trap to GDB (if
there is one attached) instead of bailing out immediately.

The obvious use-case for this, is the ability to debug guest crashes
in GDB in the standard manner.

The less-trivial use-case is for development of software in an
incomplete software stack (cf. Aarno-Engblom's "Virtual Platforms"
pp.105 et seq.)  One particular example is Ingalls-Miranda simulation of
JIT compilers, where the VM's address space may be split between the
simulated and the real machine: in this case, GDB traps facilitate the
transparent illusion of an unbroken address space.

Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44685
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 11:14:30 +00:00
Giacomo Travaglini
a2c9213a31 configs, tests: Replace optparse with argparse
JIRA: https://gem5.atlassian.net/browse/GEM5-543

Change-Id: I997d6a4e45319a74e21bd0d61d4af6118474c849
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44513
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-21 20:42:37 +00:00
Giacomo Travaglini
09b9512acd configs: restore_simpoint_checkpoint should be a boolean
The --restore_simpoint_checkpoint option is a boolean;
however if no default value is supplied, optparse sets the
default value to None

This is not valid for argparse. Argparse recognizes the store_true
action and it is automatically treating the option as a boolean,
hence providing a default=False instead of default=None

Change-Id: I6b09edf6911be71a06001730be1232a1b5c8482c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44765
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-21 20:41:44 +00:00
Hoa Nguyen
503b60ed56 configs: Fix stats name in arm/fs_power.py
In the config, there are stats having name changed:
- overall_misses -> overallMisses
- sim_seconds -> simSeconds
- overall_accesses -> overallAccesses

JIRA: https://gem5.atlassian.net/browse/GEM5-957

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I35faa72b12320e6b41833f601eb23604358b3d42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44626
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-21 09:36:07 +00:00
Giacomo Travaglini
8d5a8f01e4 util: Replace optparse with argparse
JIRA: https://gem5.atlassian.net/browse/GEM5-543

Change-Id: Id270ed29f14199f4f8eb6eb5739451a43d100484
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44512
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-21 09:05:21 +00:00
Gabe Black
2f424f6a13 sim: Track ThreadContext-s in the Workload object.
Change-Id: I00bf9fa36d3993f55d41e50196ad8a89a3d506c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44616
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
2021-04-20 07:44:19 +00:00
Gabe Black
8467e183c9 cpu,sim: Set ThreadContext's ContextID right away.
The code which registers thread contexts originally returned the ID that
it had chosen, and let the CPU actually set the ID in the object itself.
That opened a window where calling contextId() on the ThreadContext
would return the wrong answer.

Instead, we can just set the ID immediately after it's decided. This
also localizes that logic and removes plumbing for the ID between that
decision and where it's actually applied.

Change-Id: I31ad84c3f9bf6f5b6f72457ca640ea929b24f6a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44615
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-04-20 06:27:07 +00:00
Gabe Black
424eb027ff base: Add a link to documentation in the remote GDB header file.
Change-Id: I34bf4d24e58e6dfc8e8d1220a158c90fd0935e47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44608
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 04:49:33 +00:00
Gabe Black
b596aa86e2 base: Streamline the "send" method of the BaseRemoteGDB class.
The existing send method takes a const char *, but frequently the class
wants to use it to send a std::string, also frequently after generating
that string with csprintf. Rather than force each call sight to add a
.c_str() and call csprintf, this change adds helpers which will accept a
std::string and call c_str for you, or accept a format const char * and
arguments and call csprintf for you (and then call .c_str() on the
result).

Change-Id: Ifcef5e09f6469322c6040374209972528c80fb25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44607
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 04:49:14 +00:00
Gabe Black
86301ce456 cpu: Use the built in << for VecReg and VecPredReg in ExeTrace.
There's no reason to reimplement printing code when VecReg and
VecPredReg types already know how to print themselves.

Change-Id: I092c28143de286d765312122b81ce865a5184091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42001
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-04-20 00:14:09 +00:00
Gabe Black
fa505b3e12 arch: Collapse unused size parameter from "as" VecPredReg method.
Change-Id: Ibdaf38b2e2d8f37ef76d6b8874ac3620982e78a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42000
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
2d95f59ece arch,cpu: Separate printing and serialization of VecPredReg.
This is equivalent to what was done with VecReg recently.

Change-Id: I8e28c9796bf5cabd35a6bf5b89e55efcf9324d92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41999
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
eb7d3b6b6c sim: Don't needlessly recreate ISA types in InstRecord.
The ISAs already define fully realized types. We don't need to
separately track what parameters they used and then feed them into the
same templates again elsewhere.

Change-Id: Iac18bb9374ff684259c6aa00036eac4d1026dcfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42002
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:14:09 +00:00
Gabe Black
669d2c48f2 arch,mem: Use szext instead of sext as appropriate.
When the value being passed to sext needs to be masked first, szext can
be used instead without the masking.

Change-Id: I98c99ad2731216fe8ccf1253f5ac3891fe03b1de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42386
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:12:25 +00:00
Gabe Black
d5c0c638c8 arch-sparc: Fix some bit manipulation bugs.
Several sext<> calls had an off by one sign bit index, which is really
the size of the number which is being sign extended. Also, two calls in
arch/sparc/tlb.cc seemed to assume that the argument to that function
was modified in place, where really the new value is returned
separately. Move the call to sext so its return value is used and not
thrown away.

Change-Id: I86cb81ad243558e1a0d33def7f3eebe6973d6800
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42603
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:12:25 +00:00
Gabe Black
dff67336fb arch-sparc: Wrap overly long lines in the decoder definition.
Change-Id: I194f4367bd889fa6639046675b2f565a4e03bc4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42383
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:12:25 +00:00
Gabe Black
2f78ad6f7b base: Improve handling of thread IDs for remote GDB.
The remote GDB protocol encode thread IDs as positive integers, where 0
is a special value which indicates "pick any thread", and -1 is a
special value which indicates all threads.

The previous implementation would look like it worked handling the
special value -1 (for instance) because it see the '-' of "-1", stop
looking for digits, and return the default value 0.

This new implementation handles -1 as a special case, and will report an
error if no digits were found otherwise.

Also this change adds an encodeThreadId method to convert a ContextID
into a GDB thread ID by adding one to avoid the special value 0.

Change-Id: Iec54fbd9563d20a56011f48d50d69111ed1467b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44606
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:11:19 +00:00
Gabe Black
7e85c8b712 sim: Minor cleanup of the System class.
Fix style, move constant initialization out of the constructor and into
the class body, and minorly streamline an if condition.

Change-Id: I8ef42dcb8336ece58578cbd1f33937103b42989f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44605
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-20 00:11:19 +00:00
Daniel R. Carvalho
dca020e98c scons: Allow declaring dependencies of tags
It was quite incovenient to declare tags. tags either
had to be added to the Source declaration of included
files, or using (with_tag()) would need to be added
with all the indirect sub-tags. For example,

Assume:
- B.cc refers to symbols in A.cc
- C.cc refers to symbols in B.cc (i.e., it needs A transitively)
- D.cc refers to symbols in A.cc and C.cc (i.e., it needs B trans.)

So either their SConscript would be:
  Source('A.cc', add_tags=['B', 'D'])
  Source('B.cc', add_tags='B')
  Source('C.cc', add_tags='C')
  Source('D.cc', add_tags='D')

  GTest('A.test', 'A.test.cc', 'a.cc')
  GTest('B.test', 'B.test.cc', with_tag('B'))
  GTest('C.test', 'C.test.cc', with_any_tags('B', 'C'))
  GTest('D.test', 'D.test.cc', with_any_tags('B', 'C', 'D'))

or:
  Source('A.cc', add_tags=['B', 'C', 'D'])
  Source('B.cc', add_tags=['B', 'C', 'D'])
  Source('C.cc', add_tags=['C', 'D'])
  Source('D.cc', add_tags='D')

  GTest('A.test', 'A.test.cc', 'a.cc')
  GTest('B.test', 'B.test.cc', with_tag('B'))
  GTest('C.test', 'C.test.cc', with_tag('C'))
  GTest('D.test', 'D.test.cc', with_tag('D'))

This change makes it simpler. The tag should be added
only to the files directly included by the functionality
being tagged. Using the same example:

  Source('A.cc', add_tags=['B', 'D'])
  Source('B.cc', add_tags='B')
  Source('C.cc', add_tags='C')
  Source('D.cc', add_tags='D')

  env.TagImplies('B', 'A')
  env.TagImplies('C', 'B')
  env.TagImplies('D', ['A', 'C'])

  GTest('A.test', 'A.test.cc', 'a.cc')
  GTest('B.test', 'B.test.cc', with_tag('B'))
  GTest('C.test', 'C.test.cc', with_tag('C'))
  GTest('D.test', 'D.test.cc', with_tag('D'))

This also means that when a file no longer refers to
symbols from other file, or when it starts refering to
symbols from another file, one only needs to change
the dependencies of the tag directly being modified,
not the tags that rely on (imply) them. That is, on
the previous example, if C stops refering to symbols
from B, then tags that imply C do not need to be
modified:

  env.TagImplies('B','A')
  env.TagImplies('D', ['A', 'C'])

Change-Id: I5be07b01864f8d5df83f59002dfd2f01c73d5e09
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43587
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 13:44:11 +00:00
Giacomo Travaglini
fe3c2cd8a7 util: Remove unused package import
Change-Id: I67a03cffad11d4b26a193cc2c5ccb4cd30159a48
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44511
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 09:21:51 +00:00
Giacomo Travaglini
8f3e00d630 util: Fix cpt_upgrader format string
Change-Id: I9d15316f199b20976420c35d2c79dd13cc9db9ee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44510
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 09:21:51 +00:00
Giacomo Travaglini
31c9813695 configs: Remove Ruby on ARM warning
The warning was discouraging using Ruby on ARM

Change-Id: I7ccb44cdc1d32ff1258f09bc4d0d4892a758a6ef
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44509
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 09:21:51 +00:00
Yu-hsin Wang
e0ef7518c2 systemc: Extend TlmBridges to 512 bits
Change-Id: I41763743974665e78ff05203d6ad2b8ac14ad625
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44528
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-19 03:09:18 +00:00
Gabe Black
e035575ea0 scons: Move MakeAction into gem5_scons.
That will make it usable from builders defined outside of SConstruct.

Change-Id: Id1231a1a370b7d519a382db892ded93c604eb56f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40968
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-04-18 02:32:45 +00:00
Gabe Black
6ca6f41052 scons: Move the "duplicate" setting into gem5_env_defaults.py.
This is a generic default environment setting, and so should go
alongside all the other generic default environment settings.

Change-Id: If3032a4893dd84f7c7d77e7e9420436ab445cf2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40967
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-04-18 02:32:45 +00:00
Gabe Black
789b6eb615 scons: Stop piggy-backing on the default tool for default settings.
Instead, create a new tool called EnvDefaults. This tool now needs
to be explicitly listed in the set of tools available through an
Environment, but that's easy to do in on place (all environments should
stem from main). Hijacking default like we were doing was (as far as I
can tell) not how that tool was intended to be used, and doing things
this way is a bit less hacky.

Also, we can split more Builders, etc, out of SConstruct, and these will
need to attach to main in the same way. We're going to need a list of
tools when main is constructed one way or the other, so we might as well
follow the rules.

Change-Id: I392e1639cb69d373c64970dccf45258000498cc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40965
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-17 22:41:07 +00:00
Gabe Black
14f14f9a62 arch,cpu,sim: Move the null and nop StaticInstPtrs to their own files.
The nullStaticInstPtr was low overhead, but the nopStaticInstPtr needed
an actual StaticInst implementation it could point to, and that brought
with it some (minor) additional dependencies. Specifically, the
implementation of advancePC needs the definition of TheISA::PCState,
while all other signatures/impementations in StaticInst are already
passing around that type by reference or could be made to, reducing
dependencies further.

Change-Id: I9ac6a6e5a3106858ea1fc727648f61dc39738a59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42968
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-17 22:39:37 +00:00