gernhard2
beddeccb64
Fixed bug in Fifostrict that caused deadlock
2015-02-17 09:22:58 +01:00
gernhard2
f11adf51dc
Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.
...
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
2015-02-16 08:21:27 +01:00
Janik Schlemminger
f35cc43186
gute frage^^
2014-10-08 21:04:44 +02:00
Janik Schlemminger
6ce8935097
fix on fifo hack
2014-09-08 14:59:28 +02:00
Janik Schlemminger
33a13d6bfd
status quo .. jetzt wirds tricky
2014-09-07 00:04:19 +02:00
Janik Schlemminger
938dbb3fdb
print mapping
2014-09-06 20:21:43 +02:00
Janik Schlemminger
30b1fbbd0c
added no powerdown option
2014-09-06 16:59:46 +02:00
Janik Schlemminger
2aa07bbbe6
Quick and Dirty XML - Refactoring necessary
2014-09-04 23:35:54 +02:00
Janik Schlemminger
610dc6e6a5
changed fifo scheduler to strictly keep the order
2014-09-04 11:19:40 +02:00
Janik Schlemminger
df6637b114
splitting config and memspec
2014-08-29 10:25:32 +02:00
Janik Schlemminger
efc6094c13
memspec class
2014-08-27 09:43:42 +02:00
Robert Gernhardt
8e29063f76
added config for read/write grouper
2014-08-07 12:11:48 +02:00
Robert Gernhardt
b1142c4796
traceplayer can now parse data of write commands. Reorder buffer inserted
2014-08-07 12:06:04 +02:00
Janik Schlemminger
47580bcba3
added read/write grouper memconfig
2014-08-06 10:30:49 +02:00
Robert Gernhardt
767d03dfe9
modified rd/grouper
2014-08-06 10:02:56 +02:00
Robert Gernhardt
0bba004266
modified rd/write grouper
2014-08-06 09:37:42 +02:00
Janik Schlemminger
15f07b0017
precharge allchecker tRas, simulation memory
2014-08-05 19:33:16 +02:00
Janik Schlemminger
c88486d842
memcpy bug
2014-08-05 00:07:22 +02:00
Robert Gernhardt
fff7b9cd34
merged
2014-08-04 18:30:52 +02:00
Robert Gernhardt
bd245a9d90
reorder buffer
2014-08-04 18:27:33 +02:00
Janik Schlemminger
76ab26e2d7
refresh splitted in REFA REFB
2014-07-30 03:01:06 +02:00
Janik Schlemminger
c135d7c31b
Traceplayer has a clock now
2014-07-15 00:10:49 +02:00
Robert Gernhardt
c77048ac93
renamed some stuff
2014-07-14 23:17:18 +02:00
Robert Gernhardt
2b427ecb6e
also shows clks now in tooltip in analyzer
2014-07-11 09:22:34 +02:00
robert
e128263833
minor refactoring
2014-07-01 13:58:55 +02:00
robert
37c147ba2f
added debug message capabilities to scheduler
2014-07-01 11:01:52 +02:00
robert
2b062b86ff
changed scheduler interface. Fixed bug with terminateSimulation
2014-06-20 15:49:07 +02:00
robert
4760ec4a5b
adressmappings
2014-06-16 17:41:47 +02:00
robert
c74b544f3e
...
2014-05-10 13:02:55 +02:00
robert
c5512389da
changed project structure to qtcreator, added timed out powerdown
2014-05-07 17:22:20 +02:00
Matthias Jung
00f95b1587
timeout pdn (state: not runnning yet)
2014-05-05 23:24:36 +02:00
robert
cb16bd3a8a
changed simulation recorder to record filenames of memspec and memconfig
2014-05-05 10:37:59 +02:00
robert
c501985573
fixed bug in testscript
2014-04-19 14:26:50 +02:00
robert
0a7829d0ad
Changed constraints in all checkers to be generic for wideIO and ddr4
2014-04-14 02:41:04 +02:00
Janik Schlemminger
6583a661d2
tlm protocol, record in interface methods
2014-04-13 14:38:17 +02:00
