f11adf51dc
Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
26 lines
925 B
XML
26 lines
925 B
XML
<simulation>
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<simconfig>
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<Debug value="1" />
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<DatabaseRecording value="1" />
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<PowerAnalysys value="0" />
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</simconfig>
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<memspecs>
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<memspec src="/home/gernhard2/projects/dram.vp.system/dram/resources/configs/memspecs/WideIO.xml"></memspec>
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</memspecs>
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<addressmappings>
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<addressmapping src="/home/gernhard2/projects/dram.vp.system/dram/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
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</addressmappings>
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<memconfigs>
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<memconfig src="/home/gernhard2/projects/dram.vp.system/dram/resources/configs/memconfigs/fifo.xml"/>
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</memconfigs>
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<tracesetups>
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<tracesetup id="fifo">
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<!--<device clkMhz="200">test.stl</device>-->
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<device clkMhz="200">mediabench-epic_32.stl</device>
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</tracesetup>
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</tracesetups>
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</simulation>
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