Lukas Steiner (2)
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41cc447d86
|
Included timing parameters for RGR.
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2019-07-02 14:25:53 +02:00 |
|
Lukas Steiner (2)
|
ffdc67945a
|
Removed specific DRAMPower configuration in DRAMs.
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2019-07-01 15:00:01 +02:00 |
|
Lukas Steiner (2)
|
50f90176a0
|
Included specific timing parameters for different DRAMs.
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2019-07-01 11:16:36 +02:00 |
|
Lukas Steiner (2)
|
3b509a7c17
|
Marked old timing parameters with "_old" for inclusion of new ones without conflicts.
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2019-07-01 10:23:30 +02:00 |
|
Lukas Steiner
|
9b8729c58b
|
Bugfix: nbrOfRanks is only part of some memspecs for WideIO.
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2019-06-28 17:53:52 +02:00 |
|
Lukas Steiner
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409e49f044
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Bugfix: call loadCommons() only after creating a memSpec object.
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2019-06-28 17:36:51 +02:00 |
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Lukas Steiner (2)
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21adf2ac70
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Moved some timings to loadCommons().
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2019-06-28 16:26:46 +02:00 |
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Lukas Steiner (2)
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a5fb1327a1
|
Renaming of timings.
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2019-06-28 15:14:47 +02:00 |
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Lukas Steiner (2)
|
7da2aacfa3
|
Separate constructors for each DRAM type.
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2019-06-28 14:40:07 +02:00 |
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Lukas Steiner (2)
|
72152bca8b
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Included GenericController for later verilator inclusion.
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2019-06-28 14:10:09 +02:00 |
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Lukas Steiner (2)
|
ac4e4c7783
|
Moved specific timing calculation functions to MemSpecs.
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2019-06-27 16:02:24 +02:00 |
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Lukas Steiner
|
e462287d7c
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Split up timings.
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2019-06-25 22:40:18 +02:00 |
|
Lukas Steiner
|
2d08d48f81
|
Bugfix: Wrong header included. Removed redundant main function.
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2019-06-25 19:49:03 +02:00 |
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Lukas Steiner (2)
|
51e6ebfed0
|
CheckerDDR3 works, timings may still be wrong.
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2019-06-25 15:56:22 +02:00 |
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Lukas Steiner (2)
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c0d6231e26
|
Adapted timings for CheckerDDR3.
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2019-06-25 14:24:39 +02:00 |
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Lukas Steiner (2)
|
4c4119803e
|
Included CheckerDDR3.
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2019-06-25 13:37:49 +02:00 |
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Matthias Jung
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70b9ec8517
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Merge branch 'DRAMSys4.0_dev' into 'master'
Specific DRAMs and MemSpecs, renamed schedulers.
See merge request ems/astdm/dram.sys!236
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2019-06-24 16:10:33 +02:00 |
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Lukas Steiner (2)
|
188c552d5f
|
Merge remote-tracking branch 'origin/DRAMSys4.0_merge' into DRAMSys4.0_dev
# Conflicts:
# DRAMSys/library/library.pro
# DRAMSys/library/src/simulation/DRAMSys.cpp
# DRAMSys/library/src/simulation/DramDDR3.cpp
# DRAMSys/library/src/simulation/DramDDR3.h
# DRAMSys/library/src/simulation/DramDDR4.cpp
# DRAMSys/library/src/simulation/DramDDR4.h
# DRAMSys/library/src/simulation/DramRecordable.cpp
# DRAMSys/library/src/simulation/DramRecordable.h
# DRAMSys/library/src/simulation/DramWideIO.h
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2019-06-24 14:13:05 +02:00 |
|
Lukas Steiner (2)
|
d07a775697
|
Annotations for different MemSpecs.
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2019-06-24 13:59:57 +02:00 |
|
Lukas Steiner (2)
|
45b05c5cf0
|
Created DramWideIO, removed powerAnalysis switch.
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2019-06-24 11:59:59 +02:00 |
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Lukas Steiner
|
21c243b9d3
|
Replaced "BaseDram::" with "this->" to access members of the base class.
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2019-06-23 21:20:21 +02:00 |
|
Lukas Steiner
|
f8baef57c6
|
Adapting current DRAM to new structure.
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2019-06-23 20:53:08 +02:00 |
|
Lukas Steiner (2)
|
cb7b5b585a
|
NOT RUNNING! Adapting current DRAM to new structure.
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2019-06-23 19:10:28 +02:00 |
|
Lukas Steiner
|
cff2455be2
|
Bugfix for failing tests: missing renaming.
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2019-06-22 22:08:00 +02:00 |
|
Lukas Steiner
|
c3da6912a9
|
Further renaming of schedulers.
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2019-06-22 21:49:18 +02:00 |
|
Lukas Steiner
|
882a0eaa90
|
Revert "Included templates for new DRAMs."
This reverts commit 8f0e59c85e.
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2019-06-22 20:50:07 +02:00 |
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Lukas Steiner
|
27fed22003
|
Revert "Templating for DRAMs is working."
This reverts commit d69cb555ac.
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2019-06-22 20:49:57 +02:00 |
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Lukas Steiner (2)
|
d69cb555ac
|
Templating for DRAMs is working.
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2019-06-19 13:59:01 +02:00 |
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Lukas Steiner (2)
|
8f0e59c85e
|
Included templates for new DRAMs.
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2019-06-19 11:16:38 +02:00 |
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Lukas Steiner (2)
|
388a2623af
|
Preparation for merge with master.
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2019-06-18 10:52:04 +02:00 |
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Lukas Steiner (2)
|
b901c32f2a
|
Merge branch 'master' into DRAMSys4.0_dev
# Conflicts:
# DRAMSys/library/src/controller/Controller.cpp
# DRAMSys/library/src/controller/Controller.h
# DRAMSys/library/src/simulation/Dram.h
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2019-06-18 10:15:54 +02:00 |
|
Lukas Steiner
|
7540388cfe
|
Preparation for specific memspecs (member memSpec is now dynamic).
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2019-06-17 19:31:21 +02:00 |
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Lukas Steiner (2)
|
a97a20b148
|
Added specific MemSpecs, commit not running!
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2019-06-17 17:41:46 +02:00 |
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Matthias Jung
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9f253267d3
|
Merge branch 'bw_calculation_move' into 'master'
Move bandwidth calculation from DRAM to controller.
See merge request ems/astdm/dram.sys!231
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2019-06-17 10:54:12 +02:00 |
|
Lukas Steiner
|
bf1a9dc47d
|
Moved bandwidth calculation from Dram to Controller.
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2019-06-16 21:12:33 +02:00 |
|
Lukas Steiner
|
24a8f7f483
|
Code refactoring.
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2019-06-13 23:41:22 +02:00 |
|
Lukas Steiner
|
abcd2a910b
|
Renaming files (Commit 2 of 2)
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2019-06-12 20:25:38 +02:00 |
|
Lukas Steiner
|
cd67d638d4
|
Renaming files (Commit 1 of 2)
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2019-06-12 19:28:31 +02:00 |
|
Lukas Steiner
|
761bd8946f
|
Renaming files (Commit 2 of 2)
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2019-06-12 16:22:45 +02:00 |
|
Lukas Steiner
|
20797f61f5
|
Renaming files (Commit 1 of 2)
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2019-06-12 16:21:00 +02:00 |
|
Lukas Steiner
|
cea3b26bd0
|
Bugfix (incomplete renaming).
|
2019-06-12 01:49:27 +02:00 |
|
Lukas Steiner
|
6bc5f6ead3
|
Removed unused files in folder scheduler.
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2019-06-12 00:54:55 +02:00 |
|
Lukas Steiner
|
193893c23b
|
Renaming of schedulers.
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2019-06-12 00:54:02 +02:00 |
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Lukas Steiner
|
5ac2701d2c
|
Fix commit for renaming issue.
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2019-06-12 00:52:28 +02:00 |
|
Lukas Steiner
|
62c5ec720f
|
Code refactoring.
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2019-06-11 23:14:07 +02:00 |
|
Lukas Steiner
|
e7704a74e6
|
Code refactoring.
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2019-06-11 23:11:39 +02:00 |
|
Lukas Steiner
|
02803de97c
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Code refactoring.
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2019-06-11 23:10:45 +02:00 |
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Lukas Steiner
|
4454b82363
|
No changes, some TODOs for future work.
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2019-06-10 00:52:26 +02:00 |
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Lukas Steiner (2)
|
84bd62a781
|
No changes, some TODOs for future work.
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2019-06-05 16:21:26 +02:00 |
|
Lukas Steiner (2)
|
b90784f54c
|
Created cpp file for arbiter. Removed redundant routing table in arbiter.
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2019-06-04 15:51:35 +02:00 |
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