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ea6a659adc14fac94fc6a2fce95b3ede32ef27ae
gem5/src/arch/x86
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Gabe Black ea6a659adc arch-x86: Detect when entering virtual 8086 mode. 
If we're entering virtual 8086 mode, panic. Some aspects of that mode
may actually work, but since it's essentially untested, lets be extra
cautious.

Change-Id: I78bbfcb75db8370f4271c75caabc0ec53f75a884
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55810
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-14 09:56:09 +00:00
..
bare_metal
arch-x86: Bare metal workload.
2022-01-15 08:40:06 +00:00
bios
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
insts
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
isa
arch-x86: Fix a bug in the protected mode IRET.
2022-03-14 09:54:15 +00:00
kvm
arch-x86: Propogate the unusable bit to KVM.
2022-02-23 19:57:13 +00:00
linux
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
regs
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
AtomicSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
cpuid.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cpuid.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder_tables.cc
arch-x86: Fix the immediate size for the 0x9a one byte opcode.
2022-03-05 04:40:07 +00:00
decoder.cc
arch-x86: Don't decode SIB bytes in 32 bit mode.
2022-03-05 04:39:51 +00:00
decoder.hh
arch-x86: Use different tables for 64 bit prefixes in the decoder.
2022-02-26 02:00:06 +00:00
emulenv.cc
arch-x86: Correct how default segments are handled.
2022-03-05 04:39:17 +00:00
emulenv.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
faults.cc
arch-x86: Subtract the base from the PC when entering faults.
2022-03-11 22:50:10 +00:00
faults.hh
arch-x86: Get rid of the soft int Fault class.
2022-03-11 22:49:50 +00:00
fs_workload.cc
arch-x86: Respect LDT and TR bases in long mode.
2022-02-23 19:57:13 +00:00
fs_workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
interrupts.cc
arch-x86: Implement the LINT0 pin for the LAPIC.
2022-03-12 04:22:48 +00:00
interrupts.hh
arch-x86: Implement the LINT0 pin for the LAPIC.
2022-03-12 04:22:48 +00:00
intmessage.hh
arch-x86,dev: Use INTA to get the vector for the IO APIC.
2022-03-12 04:22:48 +00:00
isa.cc
arch-x86: Detect when entering virtual 8086 mode.
2022-03-14 09:56:09 +00:00
isa.hh
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
ldstflags.hh
arch-x86: Overhaul how address size is handled, particularly for stack.
2022-02-26 01:58:23 +00:00
memhelpers.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
microcode_rom.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
nativetrace.cc
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
nativetrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
NonCachingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
O3CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
arch-x86: Fix writing back 32 bit PTEs in the walker.
2022-03-14 09:55:32 +00:00
pagetable_walker.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch,cpu: Make branching() a virtual member of PCStateBase.
2021-11-30 23:30:06 +00:00
process.cc
arch-x86: Use the seg unusable bit and not a null selector in the TLB.
2022-02-14 21:42:05 +00:00
process.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pseudo_inst_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
remote_gdb.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
remote_gdb.hh
base: Correct checkBpLen naming with checkBpKind
2021-12-16 13:26:39 +00:00
SConscript
arch-x86: Bare metal workload.
2022-01-15 08:40:06 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
se_workload.hh
arch-x86: Make x86 respect m5op_base in SE mode.
2022-01-15 12:27:19 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
tlb.cc
arch-x86: Overhaul how address size is handled, particularly for stack.
2022-02-26 01:58:23 +00:00
tlb.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
types.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
types.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
vecregs.hh
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
x86_traits.hh
arch-x86,dev: Add an INTA like transaction for I8259.
2022-03-12 04:22:48 +00:00
X86CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
X86Decoder.py
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
X86FsWorkload.py
arch-x86: Bare metal workload.
2022-01-15 08:40:06 +00:00
X86ISA.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86LocalApic.py
arch-x86: Implement the LINT0 pin for the LAPIC.
2022-03-12 04:22:48 +00:00
X86MMU.py
arch: Add TypeTLB Param in BaseTLB
2021-07-28 08:13:09 +00:00
X86NativeTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86SeWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86TLB.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00