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a658ea043f9c3d5c338bcd672a5f050f52d45ca6
gem5/src/dev
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Daniel R. Carvalho a658ea043f base,dev,mem-ruby: Rename m5 namespace as gem5 
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::m5 became ::gem5.

Change-Id: I250b4354113fcd6005dc4144ae378552cb8f6717
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45437
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
..
amdgpu
misc: Replace M5_VAR_USED with GEM5_VAR_USED.
2021-05-11 20:16:31 +00:00
arm
base,dev,mem-ruby: Rename m5 namespace as gem5
2021-05-29 11:13:49 +00:00
hsa
misc: Replace M5_VAR_USED with GEM5_VAR_USED.
2021-05-11 20:16:31 +00:00
i2c
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
mips
misc: Rename SimClock namespace as sim_clock
2021-05-26 22:30:33 +00:00
net
base,dev,python: Rename Net namespace as networking
2021-05-29 11:13:49 +00:00
pci
base-stats: Rename Units namespace as units
2021-05-26 22:30:33 +00:00
ps2
dev: Rename Mouse namespace as mouse
2021-05-26 23:08:21 +00:00
riscv
arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
2021-05-07 19:36:08 +00:00
serial
sim,misc: Rename Int namespace as as_int
2021-05-26 23:08:21 +00:00
sparc
arch,dev,gpu-compute,sim: Rename isa_traits.hh page_size.hh.
2021-03-30 10:17:48 +00:00
storage
base,dev: Rename major and minor variables
2021-05-29 11:13:49 +00:00
virtio
misc: Add missing compiler.hh include
2021-05-14 10:02:14 +00:00
x86
misc: Rename Enums namespace as enums
2021-05-29 11:13:49 +00:00
baddev.cc
dev: Stop "using namespace std"
2021-01-23 12:09:51 +00:00
baddev.hh
misc: Remove unused params() definitions
2021-02-19 23:27:34 +00:00
BadDevice.py
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
Device.py
arch-arm, dev-arm: Remove Python 2 compatibility code
2021-01-22 11:05:01 +00:00
dma_device.cc
cpu,mem: Rename ContextSwitchTaskId namespace
2021-05-29 11:13:49 +00:00
dma_device.hh
dev: Use regular atomic accesses for DMA in bypass mode.
2021-01-13 01:29:32 +00:00
intel_8254_timer.cc
sim,misc: Rename Float namespace as as_float
2021-05-26 23:08:21 +00:00
intel_8254_timer.hh
misc: Fix coding style for enum's opening braces
2021-03-23 16:26:04 +00:00
intpin.cc
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
intpin.hh
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
IntPin.py
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
io_device.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
io_device.hh
misc: Remove unused params() definitions
2021-02-19 23:27:34 +00:00
isa_fake.cc
dev: Stop "using namespace std"
2021-01-23 12:09:51 +00:00
isa_fake.hh
misc: Use PARAMS
2021-02-19 23:27:34 +00:00
mc146818.cc
sim,misc: Rename Int namespace as as_int
2021-05-26 23:08:21 +00:00
mc146818.hh
sim,misc: Rename Int namespace as as_int
2021-05-26 23:08:21 +00:00
pixelpump.cc
dev: Let the pixel pump bypass the DMA FIFO in non-caching mode.
2021-01-13 23:23:59 +00:00
pixelpump.hh
dev: Let the pixel pump bypass the DMA FIFO in non-caching mode.
2021-01-13 23:23:59 +00:00
platform.cc
dev,cpu,configs: Get rid of the IntrControl device.
2021-03-29 20:54:16 +00:00
platform.hh
dev,cpu,configs: Get rid of the IntrControl device.
2021-03-29 20:54:16 +00:00
Platform.py
dev,cpu,configs: Get rid of the IntrControl device.
2021-03-29 20:54:16 +00:00
reg_bank.hh
dev: Fix compilation errors
2021-04-12 12:23:34 +00:00
reg_bank.test.cc
dev: Fix compilation errors
2021-04-12 12:23:34 +00:00
rtcreg.h
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
SConscript
dev: Add a new RegisterBank which helps handle device registers.
2020-11-01 13:08:26 +00:00