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arch-arm, dev-arm: Remove Python 2 compatibility code

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Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39580
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Andreas Sandberg
2021-01-21 16:44:16 +00:00
parent 68fe6fa6cb
commit 75e7f18e80
5 changed files with 7 additions and 7 deletions
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2
src/arch/arm/ArmSystem.py
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@@ -108,7 +108,7 @@ class ArmSystem(System):
# root instead of appended.
def generateMemNode(mem_range):
node = FdtNode("memory@%x" % long(mem_range.start))
node = FdtNode("memory@%x" % int(mem_range.start))
node.append(FdtPropertyStrings("device_type", ["memory"]))
node.append(FdtPropertyWords("reg",
state.addrCells(mem_range.start) +

2
src/dev/Device.py
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@@ -51,7 +51,7 @@ class PioDevice(ClockedObject):
def generateBasicPioDeviceNode(self, state, name, pio_addr,
size, interrupts = None):
node = FdtNode("%s@%x" % (name, long(pio_addr)))
node = FdtNode("%s@%x" % (name, int(pio_addr)))
node.append(FdtPropertyWords("reg",
state.addrCells(pio_addr) +
state.sizeCells(size) ))

6
src/dev/arm/RealView.py
View File

@@ -211,7 +211,7 @@ class RealViewCtrl(BasicPioDevice):
idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
def generateDeviceTree(self, state):
node = FdtNode("sysreg@%x" % long(self.pio_addr))
node = FdtNode("sysreg@%x" % int(self.pio_addr))
node.appendCompatible("arm,vexpress-sysreg")
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@ class RealViewOsc(ClockDomain):
def generateDeviceTree(self, state):
phandle = state.phandle(self)
node = FdtNode("osc@" + format(long(phandle), 'x'))
node = FdtNode("osc@" + format(int(phandle), 'x'))
node.appendCompatible("arm,vexpress-osc")
node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
[0x1, int(self.device)]))
@@ -595,7 +595,7 @@ class MmioSRAM(ParentMem):
super(MmioSRAM, self).__init__(**kwargs)
def generateDeviceTree(self, state):
node = FdtNode("sram@%x" % long(self.range.start))
node = FdtNode("sram@%x" % int(self.range.start))
node.appendCompatible(["mmio-sram"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.range.start) +

2
src/dev/arm/SMMUv3.py
View File

@@ -187,7 +187,7 @@ class SMMUv3(ClockedObject):
def generateDeviceTree(self, state):
reg_addr = self.reg_map.start
reg_size = self.reg_map.size()
node = FdtNode("smmuv3@%x" % long(reg_addr))
node = FdtNode("smmuv3@%x" % int(reg_addr))
node.appendCompatible("arm,smmu-v3")
node.append(FdtPropertyWords("reg",
state.addrCells(reg_addr) +

2
src/dev/arm/css/MHU.py
View File

@@ -89,7 +89,7 @@ class MHU(BasicPioDevice):
scp = Param.Scp(Parent.any, "System Control Processor")
def generateDeviceTree(self, state):
node = FdtNode("mailbox@%x" % long(self.pio_addr))
node = FdtNode("mailbox@%x" % int(self.pio_addr))
node.appendCompatible(["arm,mhu", "arm,primecell"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +