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5bf88bf7a1ab63b9e588017e7698ae3c28404eee
gem5/src/arch/riscv
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Earl Ou 5bf88bf7a1 sim: allow specifying remote gdb port for each workload 
In a platform with multiple systems, we may want to specify the
remote gdb port for each system. This change makes it
possible to specify the port number at each Workload instance.

Change-Id: I755b3960ee920ae5289819aa05d98902614a5615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65151
Maintainer: Earl Ou <shunhsingou@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-11-03 05:34:09 +00:00
..
bare_metal
sim: allow specifying remote gdb port for each workload
2022-11-03 05:34:09 +00:00
gdb-xml
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
insts
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
isa
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
linux
sim: allow specifying remote gdb port for each workload
2022-11-03 05:34:09 +00:00
regs
arch-riscv: Make ISA class the source of CSR info
2022-09-02 01:32:13 +00:00
decoder.cc
arch-riscv: rvc instruction is mistaken as branch
2021-12-22 23:51:50 +00:00
decoder.hh
arch: Make the (read|set)MiscReg methods virtual.
2022-08-20 01:15:23 +00:00
faults.cc
sim, arch-riscv: Remove Fault debug flag
2022-04-28 08:52:49 +00:00
faults.hh
arch-riscv: Make WFI halt the hart
2022-07-21 06:40:59 +00:00
fp_inst.hh
arch-riscv: When an inst generates a fault, return it immediately.
2021-05-20 23:42:13 +00:00
idle_event.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
idle_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.hh
arch-riscv: Make WFI halt the hart
2022-07-21 06:40:59 +00:00
isa.cc
arch-riscv: Add flag for misaligned access check
2022-09-14 02:22:47 +00:00
isa.hh
arch-riscv: Add flag for misaligned access check
2022-09-14 02:22:47 +00:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
arch-riscv: fix memory leak problem in page table walker
2022-02-19 11:49:44 +00:00
pagetable_walker.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch,cpu: Make branching() a virtual member of PCStateBase.
2021-11-30 23:30:06 +00:00
pma_checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pma_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PMAChecker.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
pmp.cc
arch-riscv: Fixed a bug in pmp.cc
2021-09-03 16:54:56 +00:00
pmp.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
PMP.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
pra_constants.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
arch-riscv: Revamp int regs.
2022-06-20 04:03:52 +00:00
process.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_abi.cc
arch: Switch the generic register ABI over to use RegId.
2022-06-19 07:48:14 +00:00
reg_abi.hh
arch: Switch the generic register ABI over to use RegId.
2022-06-19 07:48:14 +00:00
remote_gdb.cc
arch: Minimize use of RegClassType constants and the RegId constructor.
2022-07-27 10:59:07 +00:00
remote_gdb.hh
arch-riscv: Revamp float regs.
2022-06-20 04:04:05 +00:00
RiscvCPU.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvDecoder.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvFsWorkload.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvInterrupts.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvISA.py
arch-riscv: Add flag for misaligned access check
2022-09-14 02:22:47 +00:00
RiscvMMU.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvSeWorkload.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvTLB.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
rvk.hh
arch-riscv: Add K extension
2022-07-08 00:08:01 +00:00
SConscript
arch: Decentralize the arch tag TagImplies in arch/SConscript.
2022-09-02 10:20:51 +00:00
SConsopts
misc: Replace TARGET_ISA with USE_${ISA} variables.
2022-09-02 10:20:51 +00:00
se_workload.hh
sim: allow specifying remote gdb port for each workload
2022-11-03 05:34:09 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
tlb.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
tlb.hh
arch-riscv: Remove unused stats
2021-09-09 15:01:38 +00:00
types.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.hh
arch-riscv: Treat InvalidRegClass as zero register.
2022-07-08 00:09:01 +00:00