arch-riscv: rvc instruction is mistaken as branch

Fetch in O3CPU mistakes the normal non-branching compressed
instructions, and regards it as a branch. This issue interrupts
the consecutive instruction stream, thus affecting performance
of cpu front-end.
This fix sets the compressed for PCState during decoding.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1137

Change-Id: I7607d563bba8a08869e104877fc3c11c94cbe904
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54644
Reviewed-by: Jin Cui <cuijinbird@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/decoder.cc

@@ -105,8 +105,10 @@ Decoder::decode(PCStateBase &_next_pc)
 
     if (compressed(emi)) {
         next_pc.npc(next_pc.instAddr() + sizeof(machInst) / 2);
+        next_pc.compressed(true);
     } else {
         next_pc.npc(next_pc.instAddr() + sizeof(machInst));
+        next_pc.compressed(false);
     }
 
     return decode(emi, next_pc.instAddr());