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gem5/src/arch/riscv
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ksco 53009f9e69 arch-riscv: Add Zfh extension 
This commit adds RISC-V Zfh 1.0 (half-precision IEEE 754 binary16 floating
point) extension to gem5. Include the following commands:

* FLH / FSH
* FMADD.H / FMSUB.H / FNMSUB.H / FNMADD.H
* FADD.H / FSUB.H / FMUL.H / FDIV.H
* FSQRT.H
* FSGNJ.H / FSGNJN.H / FSGNJX.H
* FMIN.H / FMAX.H
* FCVT.S.H / FCVT.H.S
* FCVT.D.H / FCVT.H.D
* FCVT.W.H / FCVT.H.W
* FCVT.WU.H / FCVT.H.WU
* FMV.X.H / FMV.H.X
* FEQ.H / FLT.H / FLE.H
* FCLASS.H
* FCVT.L.H / FCVT.H.L
* FCVT.LU.H / FCVT.H.LU

Change-Id: Id7870fdfa1aa8b840706c3ba2cab8eeaf008880f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60029
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-27 01:22:31 +00:00
..
bare_metal
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
gdb-xml
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
insts
arch-riscv: RISCV call/ret instructions aren't decoded correctly
2022-04-21 06:34:40 +00:00
isa
arch-riscv: Add Zfh extension
2022-05-27 01:22:31 +00:00
linux
sim-se: add getrandom() syscall support
2022-03-22 02:05:32 +00:00
regs
arch-riscv: Add Zfh extension
2022-05-27 01:22:31 +00:00
AtomicSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
decoder.cc
arch-riscv: rvc instruction is mistaken as branch
2021-12-22 23:51:50 +00:00
decoder.hh
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
faults.cc
sim, arch-riscv: Remove Fault debug flag
2022-04-28 08:52:49 +00:00
faults.hh
arch,cpu: Convert ExecContext::pcState to use PCStateBase.
2021-11-29 22:00:54 +00:00
fp_inst.hh
arch-riscv: When an inst generates a fault, return it immediately.
2021-05-20 23:42:13 +00:00
idle_event.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
idle_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.hh
arch-riscv: Add NMI support
2021-11-10 06:29:33 +00:00
isa.cc
cpu,arch: Attach a debug flag to each RegClass.
2022-02-24 00:10:17 +00:00
isa.hh
arch-riscv: Add an ostream operator for PrivilegeMode
2022-01-13 10:44:48 +00:00
MinorCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
NonCachingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
O3CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
arch-riscv: fix memory leak problem in page table walker
2022-02-19 11:49:44 +00:00
pagetable_walker.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch,cpu: Make branching() a virtual member of PCStateBase.
2021-11-30 23:30:06 +00:00
pma_checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pma_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PMAChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pmp.cc
arch-riscv: Fixed a bug in pmp.cc
2021-09-03 16:54:56 +00:00
pmp.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
PMP.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pra_constants.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
process.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_abi.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
remote_gdb.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
remote_gdb.hh
base: Correct checkBpLen naming with checkBpKind
2021-12-16 13:26:39 +00:00
RiscvCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
RiscvDecoder.py
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
RiscvFsWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvInterrupts.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvISA.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvMMU.py
arch: Add TypeTLB Param in BaseTLB
2021-07-28 08:13:09 +00:00
RiscvSeWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvTLB.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SConscript
scons: Put all config variables in an env['CONF'] sub-dict.
2022-03-28 20:31:21 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
se_workload.hh
arch,sim-se: Handle syscall retry/suppression in the syscall desc.
2021-12-13 20:31:51 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
tlb.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
tlb.hh
arch-riscv: Remove unused stats
2021-09-09 15:01:38 +00:00
types.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
vecregs.hh
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00