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1323 Commits

Author SHA1 Message Date
Giacomo Travaglini
404b86813e dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache 
Otherwise a hit after a table walk will result in a 0 value being
read from the ConfigCache.

Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-25 12:49:12 +00:00
Giacomo Travaglini
e71e2d6a35 dev-arm: SMMUv3 Table walks using TnSZ 
TnSZ is needed when selecting the starting level of a table
walk, since it directly affects the number of IA bits.
This has been implemented by adding T0SZ and S2T0SZ to the
translation context.
T1SZ is not used at the moment since the current model doesn't
support TTB1.

Change-Id: I75663475c4dc01e5986cd93f8deafcdf7b1ece82
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-25 12:49:12 +00:00
Giacomo Travaglini
36da743e0b dev-arm: Use override keyword for SMMUv3 PTOPS 
Replacing the "virtual" keyword

Change-Id: I0e7b4b683ea222827a67c3a81f0deea0e906c7e5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-25 12:49:12 +00:00
Michiel Van Tol
3ed50acb1e dev-arm: Add 16K granule support to SMMUv3 model 
Added the necessary PageTableOps that match the 16K granule
translation regime.

Change-Id: I46ef07939cb4bdc8c0bbbeeeb6a50a9ab0d64de0
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19628
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-25 12:49:12 +00:00
Matteo Andreozzi
ab6001488f dev-arm: clang compatibility fix, added missing overrides 
Change-Id: I5ee5ff788570178bb1d68878a26ac9e3ce636d8e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19588
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-19 15:43:44 +00:00
Giacomo Travaglini
93fadbcabe dev-arm: Fix SMMUv3 ContextDescriptor pointer shift 
The context descriptor pointer in the STE starts at the sixth LSB

Change-Id: Ifa346b350785b788e9d1e093b662cb26433adfb8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Christo Smallwood <christo.smallwood@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19469
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-16 13:17:04 +00:00
Tiago Muck
42f32d159b dev-arm: A9SCU fixup 
Shifting instead of expensive power.

Change-Id: I164933257db125e18721c5b8bcaf9702030ebf40
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-10 19:36:34 +00:00
Giacomo Travaglini
4c38c7c02a dev-arm: Use global import path for MemObject 
Change-Id: I66e0ca6df689ec6aeb831ef5545e8e5842bb0418
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19348
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-07-01 09:42:59 +00:00
Giacomo Travaglini
0f50b6252b dev-arm: Remove un-needed Q_CONS_PROD_MASK macro 
Change-Id: I858d7eea088bbdd2dc12123e21e59991c896597f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19310
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-06-26 11:58:55 +00:00
Adrian Herrera
f82f1dd81b dev-arm: drain implementation for SMMUv3 
SMMUv3 is drained when (1) no SMMU translations are pending
on any of its slave interfaces and (2) no commands are stored
in the Command Queue waiting to be processed.

Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-06-26 11:58:55 +00:00
Adrian Herrera
09bc8b6f11 dev-arm: pending SMMU transl update on constructor/destructor 
Change-Id: I6f61651123aab129cfbe5a88aa6355cd21544a5e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19308
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-06-26 11:58:55 +00:00
Giacomo Travaglini
d3accb8ba3 dev-arm: Reapply GICv3 changes that were lost during refactoring 
The GICv3 code refactoring performed by:

https://gem5-review.googlesource.com/c/public/gem5/+/16484

reverted the following patches

https://gem5-review.googlesource.com/c/public/gem5/+/16544
https://gem5-review.googlesource.com/c/public/gem5/+/16545/3

This commit is reintroducing them

Change-Id: I2c875c11570ed66ec9203449446faca3864c64d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19229
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-06-17 08:18:45 +00:00
Stanislaw Czerniawski
2574dc41a6 dev-arm: Implement a SMMUv3 model 
This is an implementation of the SMMUv3 architecture.

What can it do?
- Single-stage and nested translation with 4k or 64k granule.  16k would
  be straightforward to add.
- Large pages are supported.
- Works with any gem5 device as long as it is issuing packets with a
  valid (Sub)StreamId

What it can't do?
- Fragment stage 1 page when the underlying stage 2 page is smaller.  S1
  page size > S2 page size is not supported
- Invalidations take zero time. This wouldn't be hard to fix.
- Checkpointing is not supported
- Stall/resume for faulting transactions is not supported

Additional contributors:
- Michiel W. van Tol <Michiel.VanTol@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19008
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-06-06 21:53:38 +00:00
Gabe Black
8666440499 arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods. 
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-05-29 04:23:46 +00:00
Giacomo Travaglini
5830ee78b6 dev-arm: Provide a GICv3 ITS Implementation 
This patch introduces the GICv3 ITS module, which is in charge of
translating MSIs into physical (GICv3) and virtual (GICv4) LPIs.  The
patch is only GICv3 compliant, which means that there is no direct
virtual LPI injection (this also means V* commands are unimplemented)
Other missing features are:

* No 2level ITS tables (only flat table supported)

* Command errors: when there is an error in the ITS, it is
IMPLEMENTATION DEFINED on how the ITS behaves.  There are three possible
scenarios (see GICv3 TRM) and this implementation only supports one of
these (which is, aborting the command and jumping to the next one).
Furter patches could make it possible to select different reactions

* Invalidation commands (INV, INVALL) are only doing the memory table
walks, assuming the current Gicv3Redistributor is not caching any
configuration table entry.

Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-22 15:17:15 +00:00
Gabe Black
972c38b1cc arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. 
This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-18 10:20:20 +00:00
Giacomo Travaglini
b6d60e82dd dev: StreamID generation in DMA device 
This patch is adding a StreamID tag to any DMA Packet. StreamIDs are
tags which are used by IOMMUs to distinguish between different
devices/functions.

For PCI devices for example, the RID (Pci Bus number, Pci Device
number, Pci Function number) could be stored in the Packet streamID
field.

For the DmaDevice base class, a simple pair of (Sub)StreamIDs has been
provided.  This is basically attaching a fixed (decided at python config
time) streamID per device.  If a derived device wants to implement a
more elaborate packet tagger (for example if it wants to have more than
one streamID), it needs to pass a different StreamID and SubstreamID to
the DmaPort interface (like dmaAction).

Change-Id: Ia17cf00437f7d3eb79211c1374134b174f90de59
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16749
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-03 08:38:12 +00:00
Giacomo Travaglini
49a71ca1d0 dev-arm: Store a PhysProxy port in Gicv3Redist 
This spares us from retrieving the TC pointer every time we want to
write/read to memory (LPIs)

Change-Id: Iad76b5e69188fa0ac5c6777a3b2664b0fc66b12f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18600
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 14:42:42 +00:00
Giacomo Travaglini
3762721456 dev-arm: Add named variable for GICD_TYPER.IDBits 
This could be used by other GICv3 components to query the maximum
number of implemented interrupt identifiers

Change-Id: I132e50de331aea22523260bcefba7e961b53eccd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18599
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 14:42:42 +00:00
Giacomo Travaglini
5c891178b9 dev-arm: Read correct version of ICC_BPR register 
Some methods like groupPriorityMask check for the value of binary point
registers. Those registers have a minimum value.  Writing to those
register is taking this into account, but the problem with the minimum
value arises when the value is checked before sw is writing to them.
In this case the minimum value won't be considered if the read is
directly forwarded to the ISA class.

Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18598
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 14:42:42 +00:00
Giacomo Travaglini
5f29ec8a5e dev-arm: Get a Gicv3Redistributor ptr from phys address 
The patch is adding the following method to Gicv3:

* Gicv3::getRedistributorByAddr
This will be needed by the ITS when trying to select the target
redistributor after decoding the collection table entry (RDBase).

Change-Id: I40e2c155f2fdc8ca6d3c20ff7a27702e02499f20
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18597
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 14:42:42 +00:00
Giacomo Travaglini
68f2f1c5f5 dev-arm: Add several LPI methods in Gicv3Redistributor 
Refactoring the existing in code in smaller methods will be crucial when
adding the ITS module, which is a client for the redistributor class and
which will require it to take different actions depending on the command
it receives from software.

List of methods:

* read/writeEntryLPI
Reading/Writing a byte from the LPI pending table

* isPendingLPI
Checks if the pINTID LPI is set. Knowing if an LPI is set is needed by
the MOVI command, which is transfering the pending state from one
redistributor to the other only if the LPI is pending.

Change-Id: If14b1c28ff7f2aa20b12dcd822bf6a490cbe0270
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18596
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 14:42:42 +00:00
Giacomo Travaglini
c16b504299 dev-arm: Take LPIs into account when interacting with CPUIF regs 
Previous code was not handling LPIs when it came to
activation/deactivation of interrupts.

Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18595
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 14:33:22 +00:00
Giacomo Travaglini
7ad6c8031a dev-arm: Fix GICv3 LPIs priority value 
Priority bits in the LPI configuration table entry are only the MSBits
([7:2]) and need to be shifted in order to get the real LPI priority
value.

Change-Id: Id04dd4fa9113a32712c73a7094df498de3c0d2b5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18594
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 12:44:13 +00:00
Giacomo Travaglini
a4f30167f6 dev-arm: Disable LPI Configuration Table caching 
This is done since caching is not done correctly, and we don't care for
now about performance degradations since the redistributor is using
PhysProxy ports.
Caching will make sense once the magical accesses will be replaced by
real atomic/timing transactions.

Change-Id: Iafe2a7843210111efc82c265bd0d5ec3cd9abb5a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18593
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 12:44:13 +00:00
Giacomo Travaglini
afce68658c dev-arm: Check EnableLPIs before checking for pending LPIs 
Before reading the tables, GICR_PENDBASER and GICR_PROPBASER need to be
properly set, and those will have a consistent value only once sw
enables LPIs.

Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18592
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 12:44:13 +00:00
Giacomo Travaglini
bc300d3112 dev-arm: GICv3 LPI tables are using physical addresses 
Change-Id: I439112f318720ae74c43a374fd3a524c607b3a23
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18591
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 12:44:13 +00:00
Giacomo Travaglini
2df87bc1fd dev-arm: Fix GICv3 LPI loop 
Loop was mistakenly increasing the upper bound of the iteration rather
than the index variable itself.

Change-Id: I0a5a7bc189bc0954a8a6d9581032c2ed902030da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18590
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 12:44:13 +00:00
Giacomo Travaglini
9de1f75f16 dev-arm: Fix Bitwise operation in GICv3 
GICv3 LPI code is wrongly using the xor operator (^) in order to
evaluate powers of two.

Change-Id: Ib1131fd5940d334967a3741f8fd15d86625be356
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18589
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-05-02 12:44:13 +00:00
Gabe Black
f19884d5ca sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh. 
Those types aren't generic or used outside of SPARC.

Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18469
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-04-30 18:52:13 +00:00
Gabe Black
cdcc55a6a8 mem: Minimize the use of MemObject. 
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-04-28 01:19:40 +00:00
Giacomo Travaglini
40018b14a6 dev-arm: Move GICv3 (Re)Ditributor address in Realview.py 
Base addresses for GICv3's Distributor and Redistributors are
implementation defined: they depend on the platform rather than the
model. This patch is then moving dist_addr and redist_addr
initialization in Realview.py

Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-04-25 12:48:41 +00:00
Giacomo Travaglini
ed48d740e8 dev-arm: Limit number of max PE in GICv3 to 128 
This is needed since there is a problem in the memory layout of
VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping
regions when reserving space for 256 PEs.

GICv3 redistributors: 0x2c010000 - 0x30010000
PCI regions: 0x30000000 - 0x40000000

We fix this by cutting down the number of supported PEs to 128

Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-04-25 12:48:41 +00:00
Giacomo Travaglini
84c4fd063a dev-arm: Add GICv4 extension switch in GICv3 
This is currently used only for determining which is the correct
size of redistributors in memory (256KB in GICv4 and 128KB in GICv3)

Change-Id: I2c07005e97167fde03548313c9927176788f31dd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18391
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-04-25 12:48:41 +00:00
Giacomo Travaglini
c366e19e62 dev-arm: Check for maximum number of supported PE in GICv3 
This is currently set to 256

Change-Id: If7bb2847c22f29bfa0cb4ebf4a7984ee43ab4e29
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18390
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-04-25 12:48:41 +00:00
Gabe Black
77201c851e dev: Use the new Port role mechanism to make an EtherInt Port type. 
This type always uses the same "ETHERNET" role, and all connections are
symmetric and self compatible.

Change-Id: I1d060f8c098d52ae9f65c052f816bc813590ff9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18171
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-04-24 11:00:31 +00:00
Giacomo Travaglini
e7a1636889 dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt 
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-04-02 16:20:54 +00:00
Giacomo Travaglini
631bfb6d25 dev-arm: Rename GIC maintenance interrupt from ppint to maint_int 
ppint is a generic name which only reflects Arm recommendation of
assigning the maintanance interrupt to a PPI (numbered 25)

Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-27 15:20:47 +00:00
Giacomo Travaglini
e8a6811ad6 dev-arm: Fix GICv3 overflow for INTID > 256 
SPIs can get to a maximum number of 1023, so that an uint8_t is not capable
of representing all of them.

Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-27 13:29:26 +00:00
Giacomo Travaglini
e36839e778 dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0) 
For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.

Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-27 13:29:10 +00:00
Giacomo Travaglini
61f0e7e267 dev-arm: Set/Unset dma coherent mode from python 
With this patch it will be possible to automatically enable/disable the
dma-coherent property for the GenericArmPciHost autogenerated DTB.  This
has been done by adding the _dma_coherent param.

Change-Id: I1759fced74e42410462637ca77997a351314a90a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-26 12:53:44 +00:00
Andrea Mondelli
4effe34f94 misc: missing override specifier 
Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-03-23 00:05:33 +00:00
Gabe Black
d3d24835bc arch, cpu, dev, gpu, mem, sim, python: start using getPort. 
Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-19 10:22:50 +00:00
Gabe Black
7f1458bec4 mem: Move bind() and unbind() into the Port class. 
These are now pure virtual methods which more specialized port
subclasses will need to implement. The SlavePort class implements them
by ignoring them and then providing parallel functions for the
MasterPort to call. The MasterPort's methods do basically what they
did before, except now bind() uses dynamic cast to check if its peer
is of the appropriate type and also to convert it into that type before
connecting to it.

Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-19 10:21:46 +00:00
Gabe Black
6e8be00dff dev: Make EtherInt inherit from Port. 
This way a common function can return EtherInt (and master and slave
ports).

Change-Id: I1215baaad918ef0352b228877241b2b6dd2503fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-03-15 18:37:49 +00:00
Gabe Black
b482cff6c3 dev: Make the EtherDevice class inherit EtherObject. 
This avoids having to define two parallel versions of the getEthPort
function, and the complex dynamic_cast macrame in connectPorts().

Change-Id: I24c09864005ff39a049e50d7245ff17e9480edea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17029
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-15 18:13:46 +00:00
Gabe Black
f5ba0d6645 dev: Turn EtherObject into an interface class. 
This class used to drive from SimObject so that it could be derived
from to get both the interface and SimObject while still using single
inheritance.

With this change, EtherObject is now just an interface class with only
one pure virtual function which can be inherited alongside SimObject.
This makes it more flexible so that it can be used in places where you
might want a different inheritance hierarchy, for instance to inherit
from MemObject.

Change-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17028
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-15 18:12:58 +00:00
Jairo Balart
66c80fcb44 dev-arm: cleanup of gicv3 CPU interface code and fixes 
Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2019-03-14 10:54:16 +00:00
Jairo Balart
509aa2179a dev-arm: cleanup of gicv3 code 
Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2019-03-12 09:33:40 +00:00
Giacomo Travaglini
a7eebbfa69 dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads 
Reading ICV_PMR_EL1 should return the value the VMCR_EL2.VPMR bits
which are aliased to the register.

Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16545
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-03-01 15:20:24 +00:00