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dev-arm: Reapply GICv3 changes that were lost during refactoring

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The GICv3 code refactoring performed by:

https://gem5-review.googlesource.com/c/public/gem5/+/16484

reverted the following patches

https://gem5-review.googlesource.com/c/public/gem5/+/16544
https://gem5-review.googlesource.com/c/public/gem5/+/16545/3

This commit is reintroducing them

Change-Id: I2c875c11570ed66ec9203449446faca3864c64d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19229
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-01-18 10:19:16 +00:00
parent 150099426a
commit d3accb8ba3
1 changed files with 36 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -159,22 +159,36 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
}
break;
}
case MISCREG_ICV_IGRPEN0_EL1: {
ICH_VMCR_EL2 ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
value = ich_vmcr_el2.VENG0;
break;
}
// Interrupt Group 1 Enable register EL1
case MISCREG_ICC_IGRPEN1:
case MISCREG_ICC_IGRPEN1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
}
break;
}
case MISCREG_ICV_IGRPEN1_EL1: {
ICH_VMCR_EL2 ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
value = ich_vmcr_el2.VENG1;
break;
}
// Interrupt Group 1 Enable register EL3
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3:
@@ -380,7 +394,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
case MISCREG_ICC_PMR:
case MISCREG_ICC_PMR_EL1:
if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
return readMiscReg(MISCREG_ICV_PMR_EL1);
}
if (haveEL(EL3) && !inSecureState() &&
@@ -401,6 +415,14 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
break;
case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
ICH_VMCR_EL2 ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
value = ich_vmcr_el2.VPMR;
break;
}
// Interrupt Acknowledge Register 0
case MISCREG_ICC_IAR0:
case MISCREG_ICC_IAR0_EL1: {
@@ -1273,7 +1295,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
case MISCREG_ICC_PMR:
case MISCREG_ICC_PMR_EL1: {
if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
return setMiscReg(MISCREG_ICV_PMR_EL1, val);
}
val &= 0xff;
@@ -1303,6 +1325,16 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
break;
}
case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
ICH_VMCR_EL2 ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2.VPMR = val & 0xff;
isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
virtualUpdate();
return;
}
// Interrupt Group 0 Enable Register EL1
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {