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dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt

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Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2019-02-18 14:33:36 +00:00
parent 4628d87e3a
commit e7a1636889
6 changed files with 22 additions and 4 deletions
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1
src/arch/arm/isa.cc
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@@ -403,6 +403,7 @@ ISA::startup(ThreadContext *tc)
haveGICv3CPUInterface = true;
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
gicv3CpuInterface->setISA(this);
gicv3CpuInterface->setThreadContext(tc);
}
}
}

5
src/dev/arm/Gic.py
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@@ -173,3 +173,8 @@ class Gicv3(BaseGic):
"Delay for PIO r/w to redistributors")
it_lines = Param.UInt32(1020,
"Number of interrupt lines supported (max = 1020)")
maint_int = Param.ArmInterruptPin(
"HV maintenance interrupt."
"ARM strongly recommends that maintenance interrupts "
"are configured to use INTID 25 (PPI Interrupt).")

2
src/dev/arm/RealView.py
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@@ -1083,7 +1083,7 @@ class VExpress_GEM5_V1(VExpress_GEM5_V1_Base):
]
class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
gic = Gicv3()
gic = Gicv3(maint_int=ArmPPI(num=25))
def _on_chip_devices(self):
return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [

1
src/dev/arm/gic_v3.hh
View File

@@ -41,6 +41,7 @@ class Gicv3Redistributor;
class Gicv3 : public BaseGic
{
protected:
friend class Gicv3CPUInterface;
typedef Gicv3Params Params;
Gicv3Distributor * distributor;

8
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -64,6 +64,12 @@ Gicv3CPUInterface::reset()
hppi.prio = 0xff;
}
void
Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
{
maintenanceInterrupt = gic->params()->maint_int->get(tc);
}
bool
Gicv3CPUInterface::getHCREL2FMO() const
{
@@ -1985,7 +1991,7 @@ Gicv3CPUInterface::virtualUpdate()
if (ich_hcr_el2.En) {
if (maintenanceInterruptStatus()) {
redistributor->sendPPInt(25);
maintenanceInterrupt->raise();
}
}

9
src/dev/arm/gic_v3_cpu_interface.hh
View File

@@ -51,6 +51,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
Gicv3Distributor * distributor;
uint32_t cpuId;
ArmInterruptPin *maintenanceInterrupt;
BitUnion64(ICC_CTLR_EL1)
Bitfield<63, 20> res0_3;
Bitfield<19> ExtRange;
@@ -307,10 +309,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
bool isEOISplitMode() const;
bool isSecureBelowEL3() const;
ICH_MISR_EL2 maintenanceInterruptStatus() const;
RegVal readMiscReg(int misc_reg) override;
void reset();
void serialize(CheckpointOut & cp) const override;
void setMiscReg(int misc_reg, RegVal val) override;
void unserialize(CheckpointIn & cp) override;
void update();
void virtualActivateIRQ(uint32_t lrIdx);
@@ -329,6 +329,11 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
void init();
void initState();
public: // BaseISADevice
RegVal readMiscReg(int misc_reg) override;
void setMiscReg(int misc_reg, RegVal val) override;
void setThreadContext(ThreadContext *tc) override;
};
#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__