e7a1636889
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
181 lines
7.1 KiB
Python
181 lines
7.1 KiB
Python
# Copyright (c) 2012-2013, 2017-2018 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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from m5.params import *
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from m5.proxy import *
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from m5.util.fdthelper import *
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from m5.SimObject import SimObject
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from m5.objects.Device import PioDevice
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from m5.objects.Platform import Platform
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class BaseGic(PioDevice):
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type = 'BaseGic'
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abstract = True
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cxx_header = "dev/arm/base_gic.hh"
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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gicd_iidr = Param.UInt32(0,
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"Distributor Implementer Identification Register")
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gicd_pidr = Param.UInt32(0,
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"Peripheral Identification Register")
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gicc_iidr = Param.UInt32(0,
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"CPU Interface Identification Register")
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gicv_iidr = Param.UInt32(0,
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"VM CPU Interface Identification Register")
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class ArmInterruptPin(SimObject):
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type = 'ArmInterruptPin'
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "ArmInterruptPinGen"
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abstract = True
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platform = Param.Platform(Parent.any, "Platform with interrupt controller")
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num = Param.UInt32("Interrupt number in GIC")
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class ArmSPI(ArmInterruptPin):
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type = 'ArmSPI'
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "ArmSPIGen"
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class ArmPPI(ArmInterruptPin):
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type = 'ArmPPI'
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cxx_header = "dev/arm/base_gic.hh"
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cxx_class = "ArmPPIGen"
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class GicV2(BaseGic):
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type = 'GicV2'
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cxx_header = "dev/arm/gic_v2.hh"
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dist_addr = Param.Addr("Address for distributor")
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cpu_addr = Param.Addr("Address for cpu")
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cpu_size = Param.Addr(0x2000, "Size of cpu register bank")
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dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
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cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface")
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int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU")
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it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)")
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gem5_extensions = Param.Bool(False, "Enable gem5 extensions")
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class Gic400(GicV2):
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"""
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As defined in:
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"ARM Generic Interrupt Controller Architecture" version 2.0
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"CoreLink GIC-400 Generic Interrupt Controller" revision r0p1
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"""
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gicd_pidr = 0x002bb490
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gicd_iidr = 0x0200143B
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gicc_iidr = 0x0202143B
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# gicv_iidr same as gicc_idr
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gicv_iidr = gicc_iidr
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class Gicv2mFrame(SimObject):
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type = 'Gicv2mFrame'
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cxx_header = "dev/arm/gic_v2m.hh"
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spi_base = Param.UInt32(0x0, "Frame SPI base number");
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spi_len = Param.UInt32(0x0, "Frame SPI total number");
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addr = Param.Addr("Address for frame PIO")
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class Gicv2m(PioDevice):
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type = 'Gicv2m'
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cxx_header = "dev/arm/gic_v2m.hh"
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pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
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gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts")
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frames = VectorParam.Gicv2mFrame([], "Power of two number of frames")
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class VGic(PioDevice):
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type = 'VGic'
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cxx_header = "dev/arm/vgic.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
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hv_addr = Param.Addr(0, "Address for hv control")
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pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
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# The number of list registers is not currently configurable at runtime.
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maint_int = Param.UInt32("HV maintenance interrupt number")
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# gicv_iidr same as gicc_idr
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gicv_iidr = Param.UInt32(Self.gic.gicc_iidr,
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"VM CPU Interface Identification Register")
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def generateDeviceTree(self, state):
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gic = self.gic.unproxy(self)
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node = FdtNode("interrupt-controller")
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node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic",
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"arm,cortex-a9-gic"])
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node.append(FdtPropertyWords("#interrupt-cells", [3]))
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node.append(FdtPropertyWords("#address-cells", [0]))
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node.append(FdtProperty("interrupt-controller"))
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regs = (
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state.addrCells(gic.dist_addr) +
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state.sizeCells(0x1000) +
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state.addrCells(gic.cpu_addr) +
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state.sizeCells(0x1000) +
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state.addrCells(self.hv_addr) +
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state.sizeCells(0x2000) +
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state.addrCells(self.vcpu_addr) +
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state.sizeCells(0x2000) )
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node.append(FdtPropertyWords("reg", regs))
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node.append(FdtPropertyWords("interrupts",
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[1, int(self.maint_int)-16, 0xf04]))
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node.appendPhandle(gic)
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yield node
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class Gicv3(BaseGic):
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type = 'Gicv3'
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cxx_header = "dev/arm/gic_v3.hh"
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dist_addr = Param.Addr(0x2c000000, "Address for distributor")
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dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
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redist_addr = Param.Addr(0x2c010000, "Address for redistributors")
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redist_pio_delay = Param.Latency('10ns',
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"Delay for PIO r/w to redistributors")
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it_lines = Param.UInt32(1020,
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"Number of interrupt lines supported (max = 1020)")
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maint_int = Param.ArmInterruptPin(
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"HV maintenance interrupt."
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"ARM strongly recommends that maintenance interrupts "
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"are configured to use INTID 25 (PPI Interrupt).")
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