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dev: Use the new Port role mechanism to make an EtherInt Port type.

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This type always uses the same "ETHERNET" role, and all connections are
symmetric and self compatible.

Change-Id: I1d060f8c098d52ae9f65c052f816bc813590ff9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18171
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabe Black
2019-04-15 19:47:28 -07:00
parent 3c3f360bbe
commit 77201c851e
1 changed files with 17 additions and 6 deletions
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23
src/dev/net/Ethernet.py
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@@ -44,11 +44,22 @@ from m5.params import *
from m5.proxy import *
from m5.objects.PciDevice import PciDevice
ETHERNET_ROLE = 'ETHERNET'
Port.compat(ETHERNET_ROLE, ETHERNET_ROLE)
class EtherInt(Port):
def __init__(self, desc):
super(EtherInt, self).__init__(ETHERNET_ROLE, desc)
class VectorEtherInt(VectorPort):
def __init__(self, desc):
super(VectorEtherInt, self).__init__(ETHERNET_ROLE, desc)
class EtherLink(SimObject):
type = 'EtherLink'
cxx_header = "dev/net/etherlink.hh"
int0 = SlavePort("interface 0")
int1 = SlavePort("interface 1")
int0 = EtherInt("interface 0")
int1 = EtherInt("interface 1")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
speed = Param.NetworkBandwidth('1Gbps', "link speed")
@@ -57,7 +68,7 @@ class EtherLink(SimObject):
class DistEtherLink(SimObject):
type = 'DistEtherLink'
cxx_header = "dev/net/dist_etherlink.hh"
int0 = SlavePort("interface 0")
int0 = EtherInt("interface 0")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
speed = Param.NetworkBandwidth('1Gbps', "link speed")
@@ -85,7 +96,7 @@ class EtherSwitch(SimObject):
dump = Param.EtherDump(NULL, "dump object")
fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in bits "
"per second")
interface = VectorMasterPort("Ethernet Interface")
interface = VectorEtherInt("Ethernet Interface")
output_buffer_size = Param.MemorySize('1MB', "size of output port buffers")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
@@ -97,7 +108,7 @@ class EtherTapBase(SimObject):
cxx_header = "dev/net/ethertap.hh"
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
tap = SlavePort("Ethernet interface to connect to gem5's network")
tap = EtherInt("Ethernet interface to connect to gem5's network")
if buildEnv['USE_TUNTAP']:
class EtherTap(EtherTapBase):
@@ -122,7 +133,7 @@ class EtherDevice(PciDevice):
type = 'EtherDevice'
abstract = True
cxx_header = "dev/net/etherdevice.hh"
interface = MasterPort("Ethernet Interface")
interface = EtherInt("Ethernet Interface")
class IGbE(EtherDevice):
# Base class for two IGbE adapters listed above