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dev-arm: Disable LPI Configuration Table caching

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This is done since caching is not done correctly, and we don't care for
now about performance degradations since the redistributor is using
PhysProxy ports.
Caching will make sense once the magical accesses will be replaced by
real atomic/timing transactions.

Change-Id: Iafe2a7843210111efc82c265bd0d5ec3cd9abb5a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18593
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-04-25 16:31:55 +01:00
parent afce68658c
commit a4f30167f6
2 changed files with 20 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
src/dev/arm/gic_v3_redistributor.cc
View File

@@ -675,9 +675,6 @@ Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size,
lpiIDBits = 0xf;
}
uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
lpiConfigurationTable.resize(number_lpis);
break;
}
@@ -698,25 +695,12 @@ Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size,
break;
case GICR_INVLPIR: { // Redistributor Invalidate LPI Register
uint32_t lpi_id = data & 0xffffffff;
uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
if (lpi_id > largest_lpi_id) {
return;
}
uint32_t lpi_table_entry_index = lpi_id - SMALLEST_LPI_ID;
invalLpiConfig(lpi_table_entry_index);
// Do nothing: no caching supported
break;
}
case GICR_INVALLR: { // Redistributor Invalidate All Register
for (int lpi_table_entry_index = 0;
lpi_table_entry_index < lpiConfigurationTable.size();
lpi_table_entry_index++) {
invalLpiConfig(lpi_table_entry_index);
}
// Do nothing: no caching supported
break;
}
@@ -726,17 +710,6 @@ Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size,
}
}
void
Gicv3Redistributor::invalLpiConfig(uint32_t lpi_entry_index)
{
Addr lpi_table_entry_ptr = lpiConfigurationTablePtr +
lpi_entry_index * sizeof(LPIConfigurationTableEntry);
ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
tc->getPhysProxy().readBlob(lpi_table_entry_ptr,
(uint8_t*) &lpiConfigurationTable[lpi_entry_index],
sizeof(LPIConfigurationTableEntry));
}
void
Gicv3Redistributor::sendPPInt(uint32_t int_id)
{
@@ -831,13 +804,22 @@ Gicv3Redistributor::update()
// Check LPIs
if (EnableLPIs) {
const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
char lpi_pending_table[largest_lpi_id / 8];
ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
const uint32_t number_lpis = largest_lpi_id - SMALLEST_LPI_ID + 1;
uint8_t lpi_pending_table[largest_lpi_id / 8];
uint8_t lpi_config_table[number_lpis];
tc->getPhysProxy().readBlob(lpiPendingTablePtr,
(uint8_t *) lpi_pending_table,
sizeof(lpi_pending_table));
tc->getPhysProxy().readBlob(lpiConfigurationTablePtr,
(uint8_t*) lpi_config_table,
sizeof(lpi_config_table));
for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
lpi_id++) {
uint32_t lpi_pending_entry_byte = lpi_id / 8;
@@ -845,16 +827,19 @@ Gicv3Redistributor::update()
bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] &
1 << lpi_pending_entry_bit_position;
uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID;
bool lpi_is_enable =
lpiConfigurationTable[lpi_configuration_entry_index].enable;
LPIConfigurationTableEntry config_entry =
lpi_config_table[lpi_configuration_entry_index];
bool lpi_is_enable = config_entry.enable;
// LPIs are always Non-secure Group 1 interrupts,
// in a system where two Security states are enabled.
Gicv3::GroupId lpi_group = Gicv3::G1NS;
bool group_enabled = distributor->groupEnabled(lpi_group);
if (lpi_is_pending && lpi_is_enable && group_enabled) {
uint8_t lpi_priority =
lpiConfigurationTable[lpi_configuration_entry_index].priority;
uint8_t lpi_priority =config_entry.priority;
if ((lpi_priority < cpuInterface->hppi.prio) ||
(lpi_priority == cpuInterface->hppi.prio &&

3
src/dev/arm/gic_v3_redistributor.hh
View File

@@ -161,8 +161,6 @@ class Gicv3Redistributor : public Serializable
Bitfield<0> enable;
EndBitUnion(LPIConfigurationTableEntry)
std::vector<LPIConfigurationTableEntry> lpiConfigurationTable;
static const uint32_t GICR_CTLR_ENABLE_LPIS = 1 << 0;
static const uint32_t GICR_CTLR_DPG0 = 1 << 24;
static const uint32_t GICR_CTLR_DPG1NS = 1 << 25;
@@ -205,7 +203,6 @@ class Gicv3Redistributor : public Serializable
public:
Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
void invalLpiConfig(uint32_t lpi_entry_index);
uint32_t getAffinity() const;
void init();
void initState();