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dev-arm: Check EnableLPIs before checking for pending LPIs

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Before reading the tables, GICR_PENDBASER and GICR_PROPBASER need to be
properly set, and those will have a consistent value only once sw
enables LPIs.

Change-Id: Ifb87944a491045e7a13ce7a280c555cb0c1e47f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18592
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-04-26 13:21:59 +01:00
parent bc300d3112
commit afce68658c
1 changed files with 31 additions and 29 deletions
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60
src/dev/arm/gic_v3_redistributor.cc
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@@ -830,38 +830,40 @@ Gicv3Redistributor::update()
}
// Check LPIs
const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
char lpi_pending_table[largest_lpi_id / 8];
ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
tc->getPhysProxy().readBlob(lpiPendingTablePtr,
(uint8_t *) lpi_pending_table,
sizeof(lpi_pending_table));
if (EnableLPIs) {
const uint32_t largest_lpi_id = 1 << (lpiIDBits + 1);
char lpi_pending_table[largest_lpi_id / 8];
ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
tc->getPhysProxy().readBlob(lpiPendingTablePtr,
(uint8_t *) lpi_pending_table,
sizeof(lpi_pending_table));
for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
lpi_id++) {
uint32_t lpi_pending_entry_byte = lpi_id / 8;
uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] &
1 << lpi_pending_entry_bit_position;
uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID;
bool lpi_is_enable =
lpiConfigurationTable[lpi_configuration_entry_index].enable;
// LPIs are always Non-secure Group 1 interrupts,
// in a system where two Security states are enabled.
Gicv3::GroupId lpi_group = Gicv3::G1NS;
bool group_enabled = distributor->groupEnabled(lpi_group);
for (int lpi_id = SMALLEST_LPI_ID; lpi_id < largest_lpi_id;
lpi_id++) {
uint32_t lpi_pending_entry_byte = lpi_id / 8;
uint8_t lpi_pending_entry_bit_position = lpi_id % 8;
bool lpi_is_pending = lpi_pending_table[lpi_pending_entry_byte] &
1 << lpi_pending_entry_bit_position;
uint32_t lpi_configuration_entry_index = lpi_id - SMALLEST_LPI_ID;
bool lpi_is_enable =
lpiConfigurationTable[lpi_configuration_entry_index].enable;
// LPIs are always Non-secure Group 1 interrupts,
// in a system where two Security states are enabled.
Gicv3::GroupId lpi_group = Gicv3::G1NS;
bool group_enabled = distributor->groupEnabled(lpi_group);
if (lpi_is_pending && lpi_is_enable && group_enabled) {
uint8_t lpi_priority =
lpiConfigurationTable[lpi_configuration_entry_index].priority;
if (lpi_is_pending && lpi_is_enable && group_enabled) {
uint8_t lpi_priority =
lpiConfigurationTable[lpi_configuration_entry_index].priority;
if ((lpi_priority < cpuInterface->hppi.prio) ||
(lpi_priority == cpuInterface->hppi.prio &&
lpi_id < cpuInterface->hppi.intid)) {
cpuInterface->hppi.intid = lpi_id;
cpuInterface->hppi.prio = lpi_priority;
cpuInterface->hppi.group = lpi_group;
new_hppi = true;
if ((lpi_priority < cpuInterface->hppi.prio) ||
(lpi_priority == cpuInterface->hppi.prio &&
lpi_id < cpuInterface->hppi.intid)) {
cpuInterface->hppi.intid = lpi_id;
cpuInterface->hppi.prio = lpi_priority;
cpuInterface->hppi.group = lpi_group;
new_hppi = true;
}
}
}
}