derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads

Browse Source 
Reading ICV_PMR_EL1 should return the value the VMCR_EL2.VPMR bits
which are aliased to the register.

Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16545
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2019-01-18 09:43:52 +00:00
parent 5e55ecc4b5
commit a7eebbfa69
1 changed files with 23 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/dev/arm/gic_v3_cpu_interface.cc
View File

@@ -388,7 +388,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
case MISCREG_ICC_PMR_EL1: // Priority Mask Register
if ((currEL() == EL1) && !inSecureState() &&
(hcr_imo || hcr_fmo)) {
return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
return readMiscReg(MISCREG_ICV_PMR_EL1);
}
if (haveEL(EL3) && !inSecureState() &&
@@ -406,6 +406,14 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
break;
case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
value = ich_vmcr_el2 >> ICH_VMCR_EL2_VPMR_SHIFT;
break;
}
case MISCREG_ICC_IAR0:
case MISCREG_ICC_IAR0_EL1: { // Interrupt Acknowledge Register 0
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -1268,7 +1276,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
case MISCREG_ICC_PMR_EL1: { // Priority Mask Register
if ((currEL() == EL1) && !inSecureState() &&
(hcr_imo || hcr_fmo)) {
return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
return setMiscReg(MISCREG_ICV_PMR_EL1, val);
}
val &= 0xff;
@@ -1295,6 +1303,19 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
break;
}
case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2 = insertBits(
ich_vmcr_el2,
ICH_VMCR_EL2_VPMR_SHIFT + ICH_VMCR_EL2_VPMR_LENGTH - 1,
ICH_VMCR_EL2_VPMR_SHIFT, val);
isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
virtualUpdate();
return;
}
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: { // Interrupt Group 0 Enable Register
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {