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dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping on reads

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Reading ICV_IGRPEN<n>_EL1 should return the value of VMCR_EL2.VENG0 and
VMCR_EL2.VENG1 bits.

Change-Id: Ia5d748cf60ba074cccf4c127ac479c5cb881773d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16544
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2019-01-18 10:19:16 +00:00
parent 2c242d665f
commit 5e55ecc4b5
1 changed files with 16 additions and 2 deletions
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18
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -151,21 +151,35 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
}
break;
}
case MISCREG_ICV_IGRPEN0_EL1: {
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG0_SHIFT);
break;
}
case MISCREG_ICC_IGRPEN1:
case MISCREG_ICC_IGRPEN1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
}
break;
}
case MISCREG_ICV_IGRPEN1_EL1: {
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
value = bits(ich_vmcr_el2, ICH_VMCR_EL2_VENG1_SHIFT);
break;
}
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3: {
// EnableGrp1S and EnableGrp1NS are aliased with