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dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache

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Otherwise a hit after a table walk will result in a 0 value being
read from the ConfigCache.

Change-Id: I9813998acce44c93c5ce203f252ca80c10ba8f38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-07-23 16:34:26 +01:00
parent e71e2d6a35
commit 404b86813e
2 changed files with 7 additions and 0 deletions
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2
src/dev/arm/smmu_v3_caches.hh
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@@ -252,6 +252,8 @@ class ConfigCache : public SMMUv3BaseCache
uint16_t vmid;
uint8_t stage1_tg;
uint8_t stage2_tg;
uint8_t t0sz;
uint8_t s2t0sz;
};
ConfigCache(unsigned numEntries, unsigned _associativity,

5
src/dev/arm/smmu_v3_transl.cc
View File

@@ -532,6 +532,9 @@ SMMUTranslationProcess::configCacheLookup(Yield &yield, TranslContext &tc)
tc.stage1TranslGranule = e->stage1_tg;
tc.stage2TranslGranule = e->stage2_tg;
tc.t0sz = e->t0sz;
tc.s2t0sz = e->s2t0sz;
return true;
}
@@ -555,6 +558,8 @@ SMMUTranslationProcess::configCacheUpdate(Yield &yield,
e.vmid = tc.vmid;
e.stage1_tg = tc.stage1TranslGranule;
e.stage2_tg = tc.stage2TranslGranule;
e.t0sz = tc.t0sz;
e.s2t0sz = tc.s2t0sz;
doSemaphoreDown(yield, smmu.configSem);