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dev-arm: Take LPIs into account when interacting with CPUIF regs

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Previous code was not handling LPIs when it came to
activation/deactivation of interrupts.

Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18595
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-04-25 10:43:48 +01:00
parent 7ad6c8031a
commit c16b504299
2 changed files with 15 additions and 6 deletions
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18
src/dev/arm/gic_v3_cpu_interface.cc
View File

@@ -409,7 +409,8 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
int_id = getHPPIR0();
// avoid activation for special interrupts
if (int_id < Gicv3::INTID_SECURE) {
if (int_id < Gicv3::INTID_SECURE ||
int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
activateIRQ(int_id, hppi.group);
}
} else {
@@ -464,7 +465,8 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
int_id = getHPPIR1();
// avoid activation for special interrupts
if (int_id < Gicv3::INTID_SECURE) {
if (int_id < Gicv3::INTID_SECURE ||
int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
activateIRQ(int_id, hppi.group);
}
} else {
@@ -778,7 +780,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
int int_id = val & 0xffffff;
// avoid activation for special interrupts
if (int_id >= Gicv3::INTID_SECURE) {
if (int_id >= Gicv3::INTID_SECURE &&
int_id <= Gicv3::INTID_SPURIOUS) {
return;
}
@@ -847,7 +850,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
int int_id = val & 0xffffff;
// avoid deactivation for special interrupts
if (int_id >= Gicv3::INTID_SECURE) {
if (int_id >= Gicv3::INTID_SECURE &&
int_id <= Gicv3::INTID_SPURIOUS) {
return;
}
@@ -1770,6 +1774,9 @@ Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
// SPI, distributor
distributor->activateIRQ(int_id);
distributor->updateAndInformCPUInterfaces();
} else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
// LPI, Redistributor
redistributor->setClrLPI(int_id, false);
}
}
@@ -1806,7 +1813,8 @@ Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
distributor->deactivateIRQ(int_id);
distributor->updateAndInformCPUInterfaces();
} else {
return;
// LPI, redistributor, shouldn't deactivate
redistributor->updateAndInformCPUInterface();
}
}

3
src/dev/arm/gic_v3_redistributor.cc
View File

@@ -854,7 +854,8 @@ Gicv3Redistributor::update()
}
if (!new_hppi && cpuInterface->hppi.prio != 0xff &&
cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
(cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX ||
cpuInterface->hppi.intid > SMALLEST_LPI_ID)) {
distributor->fullUpdate();
}
}