Commit Graph

16817 Commits

Author SHA1 Message Date
Gabe Black
fad705680e systemc: Stop using std::gets in systemc.h.
This is in the Accellera version of systemc, used when gem5 is built
into systemc as a black box. std::gets was depdecated in c++11, and
removed entirely in c++14. Since gem5 has moved to c++14, this can't be
brought in with "using" in that header. More recent versions of systemc
from Accellera may have this fixed, and it's pretty bad practice to have
a universal header file squash unrelated namespaces like that in the
first place.

Rather tha update all of this copy of systemc, this change just makes
the smallest adjustment possible to get things to work again.

Change-Id: I8a95665d4b5d49ffc014097714cf2e602bf9b937
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42583
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 07:32:47 +00:00
Bobby R. Bruce
78b640b994 base-stats,python: Add missing "group" in _prepare_stats
Change-Id: Idb25185e1d29ac9fd8c0503d55b56e0568a61d1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42704
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 04:55:28 +00:00
Peter
48094d1abf arch-riscv: Fixing RISC-V remote GDB MIP and MIE accesses.
readMiscRegNoEffect reads directly from the misc reg file.
However, MIP and MIE actually reads directly from the
interrupt controller and does not store the values in the
misc reg file. As such, readMiscReg should be used instead.

Change-Id: I6bd71da5c83e12c06043889bdbef7e4c0cf78190
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39816
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 02:28:25 +00:00
Jason Lowe-Power
89ec39a147 python: Use Pattern from typing
Python <3.7 must import Pattern from typing not re

Change-Id: I56acb466aef40b7188e4cd58d3ba5d0b0cc9b090
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42643
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-10 20:57:53 +00:00
Yu-hsin Wang
ee1837d313 system-arm: update armv8 cpu-release-addr
In the cl below, cpu-release-addr is changed to 0x87fffff8.
https://gem5-review.googlesource.com/c/public/gem5/+/35076

By fixing cpu-release-addr, we are able to bring up multi-core platform.

Change-Id: I48bb678f67b677e9fc0136c378407e06ce7a46f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42484
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-09 02:01:25 +00:00
Giacomo Travaglini
3acc6af5c2 configs: NVM missing the xor_low_bit argument in create_mem_intf
Change-Id: Ie197cec1eaa82ca61a6bbb82c33307a16d779dbd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42321
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-08 09:50:37 +00:00
Kyle Roarty
f5383a5733 gpu-compute: Fix accidental execution when stopped at barrier
Due the compute unit pipeline being executed in reverse order, there
exists a scenario where a compute unit will execute an extra
instruction when it's supposed to be stopped at a barrier. It occurs
as follows:

* The ScheduleStage sets a barrier instruction ready to execute.

* The ScoreboardCheckStage adds another instruction to the readyList.
This is where the barrier is checked, but because the barrier isn't
executing yet, the instruction can be passed along to ScheduleStage

* The barrier executes, and stalls

* The ScheduleStage sees that there's a new instruction and schedules
it to be executed.

* Only now will the ScoreboardCheckStage realize a barrier is active
and stall accordingly

* The subsequent instruction executes

This patch sets the wavefront status to be S_BARRIER in ScheduleStage
instead of in the barrier instruction execution in order to have
ScoreboardCheckStage realize that we're going to execute a barrier,
preventing it from marking another instruciton as ready.

Change-Id: Ib683e2c68f361d7ee60a3beaf53b4b6c888c9f8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41573
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-04 17:37:19 +00:00
Giacomo Travaglini
c47920d81c arch-arm: Fix atomics permission checks in TLB
For stage 2 translations, atomic accesses were not checking the
access permission bits in the page table descriptors, and were
instead wrongly using the nature of the request itself
(r/w booleans).

Change-Id: I27fbc95f04ea659e77ad5a3afb551873c9c971f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42073
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-04 09:27:57 +00:00
Jason Lowe-Power
ef9e672eb9 python: Add search functions to pystats groups
This change adds three functions, a `children` function which will
iterate through all of the children of group based (optionally) on some
predicate. Then, it implements a `find` function and a `find_re`
function using the `children` function.

The `find` function allows users to match statistics or groups
within a group. For instance, you might want to find all of the groups
within the system which have the name "cpu{i}". This is useful for
aggregate statistic values across multiple components.

Example:
total_instruuctions = sum([cpu.exec_context.thread_0.numInsts.value
                           for cpu in simstat.system.find('cpu')])

The find function matches based on substring. If the name given the find
function is a substring of the stat name or the group name the
stat/group will be returned.

The `find_re` function is the same as find, but matches a regular
expression instead of a simple substring match.

Note: this was originally reviewed on
https://gem5-review.googlesource.com/c/public/gem5/+/41603 was rebased
incorrectly before merging. This change fixes the rebase and adds back
the children() and re_find() functions.

Change-Id: Idaa1e9efc56fd26de3285d3fa505087ddd78ac8a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42014
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-03-03 16:48:23 +00:00
Bobby R. Bruce
649e5cd8e0 python: Add search functions to pystats groups
This change adds three functions, a `children` function which will
iterate through all of the children of group based (optionally) on some
predicate. Then, it implements a `find` function and a `find_re`
function using the `children` function.

The `find` function allows users to match statistics or groups
within a group. For instance, you might want to find all of the groups
within the system which have the name "cpu{i}". This is useful for
aggregate statistic values across multiple components.

Example:
total_instruuctions = sum([cpu.exec_context.thread_0.numInsts.value
                           for cpu in simstat.system.find('cpu')])

The find function matches based on substring. If the name given the find
function is a substring of the stat name or the group name the
stat/group will be returned.

The `find_re` function is the same as find, but matches a regular
expression instead of a simple substring match.

Change-Id: I31c2a029d8a6b1d97225ab4efa34a4d13147ea32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41603
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-01 22:33:30 +00:00
Tiago Mück
3a1eadc04d configs: Ruby fixes for SimpleMemory
Change-Id: Idc21c8c616ef953d161685ec459765ef21ac9bc3
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41817
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-01 22:19:13 +00:00
Tiago Mück
5b9517f196 mem-ruby: renamed prefetch stats
Splitting hw_prefetches into prefetch_hits and prefetch_misses so both
events can be tracked separately. Also added appropriate functions to
increment stats. Renamed m_prefetches for consistency.

sw_prefetches is not used and has been removed. The sequencer converts
SW prefetch requests into a RubyRequestType_LD/RubyRequestType_ST
which are handled as demand requests by the all current protocols.

Change-Id: Iafa6b31c84843ddd1fad98fa7e5afed02b8c4b4d
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41816
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-01 22:18:59 +00:00
Tiago Mück
1a9716044a mem-ruby: notify controller on coalescing
Sequencer notifies controllers when coalescing requests.
notifyCoalesced can be overridden by protocols to, for instance,
account for coalesced requests in hit/miss stats and/or prefetcher
training.

Change-Id: Ia9c8d64cac2cd3ce859a76a1dc1324e3fc6a7b90
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41815
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-03-01 22:16:15 +00:00
Tiago Mück
f7a3d8bee4 mem-ruby: fix MI_example functional read
Changing AccessPermission to Read_Write for transient states waiting
on memory when to or from Invalid. In all cases the memory will have
the latest data, so this also modifies functionalRead to always send
the access to memory.

Change-Id: I99f557539b4f9d0d2f99558752b7ddb7e85ab3c6
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41853
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-01 22:08:25 +00:00
Kyle Roarty
a9e0a1ccf1 gpu-compute: Explicitly set driver to nullptr in constructor
We have a fail_if in attachDriver to prevent driver from being
overwritten. However, the fail_if only checks for if the driver
is not nullptr.

Previously, in some cases driver was set to garbage, which made
the fail_if trip the first time we were assigning the driver.

This patch explicitly sets driver to nullptr in the constructor, thus
ensuring that it will be nullptr the first time we call attachDriver

Change-Id: I325f6033e785025a912e3af3888c66cee0332f40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41973
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-01 18:10:11 +00:00
Mahyar Samani
17d04a7b53 cpu: Adding stridedGen
This patch adds the source code for a mode of traffic generator to
generate strided access pattern to the memory. The main difference
between a stridedGen and linearGen are in the way startAddr and
nextAddr are set. In stridedGen instead of increasing the current
address by blocksize to generate nextAddr, it is increased by
strideSize. Also, the offset param is used to indicate the order
of any instances of traffic generator in an array (similar to
threadId.x in CUDA)

Change-Id: I80df414faf1c73f68e87400654675a553de0caa5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40515
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-03-01 17:26:47 +00:00
Bobby R. Bruce
53b5ae1013 base-stats: Fixed System "work_item" stat name
The name of this stat was prefixed with 'system.'. Something which is
unecessary and undesirable for the stats output.

Change-Id: I873a77927e1ae6bb52f66e9c935e91ef43649dcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41833
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-26 20:44:47 +00:00
Bobby R. Bruce
f769117fd1 base-stats,python: Add Units to the Python Stats
Change-Id: Ic8d3c9a5c2bb7fbe51b8672b74b0e5fb17906a5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41754
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-26 20:44:47 +00:00
Bobby R. Bruce
dbbe59a0be base-stats,python: Expose a stat's unit via PyBind11
Change-Id: I77df868a6bc92e5bb0a39592b5aca8e0d259bb05
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41753
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-26 20:44:47 +00:00
Bobby R. Bruce
1a1b53b9dd sim,base-stats: Fix leading "." bug when obtaining requestors
When requestor id is requested, it is stripped of the System name via
the `stripSystemName` function in `system.cc`. However, there is a bug
in this code that leaves a leading ".". E.g.:

`system.cpu.mmu.dtb.walker` is stripped to `.cpu.mmu.dtb.walker`.

This patch fixes this issue.

Change-Id: I825cbc60c7f7eaa84c8a0150c30e9f2902cff6cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41513
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-26 20:44:47 +00:00
Bobby R. Bruce
f11617736e base-stats,python: Add Python Stats
This model is used to store and represent the "new" hierarchical stats
at the Python level. Over time these classes may be extended with
functions to ease in the analysis of gem5 stats. Though, for this
commit, such functions have been kept to a minimum.

`m5/pystats/loader.py` contains functions for translating the gem5  `_m5.stats`
statistics exposed via Pybind11 to the Python Stats model. For example:

```
import m5.pystats.gem5stats as gem5stats

simstat = gem5stats.get_simstat(root)
```

All the python Stats model classes inherit from JsonSerializable meaning
they can be translated to JSON. For example:

```
import m5.pystats.gem5stats as gem5stats

simstat = gem5stats.get_simstat(root)
with open('test.json', 'w') as f:
    simstat.dump(f)
```

The stats have also been exposed via the python statistics API. Via
command line, a JSON output may be specified with the argument
`--stats-file json://<file path>`.

Change-Id: I253a869f6b6d8c0de4dbed708892ee0cc33c5665
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38615
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-26 20:44:47 +00:00
Bobby R. Bruce
bd6e1fc9c5 arch-riscv,misc: Add missing overrides for clang compilation
The Clang compiler returns "missing override" errors without these.

Change-Id: I62af6c338b000123c924f0b3205551579bd5aeb4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41913
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-26 18:59:30 +00:00
Bobby R. Bruce
e100156a51 misc: Adding 'make' to the compiler Dockerfiles
While gem5 will compile without make, LTO cannot link on multiple
threads without it.

Change-Id: Id5552aaa295e194789ab5f355bb62a3657384d38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41873
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-25 23:19:15 +00:00
Tiago Mück
9396be08da mem-ruby: RubyRequest getter for request ptr
Change-Id: Ib3d12c9030d18d96388dd66f0a409b42543ee9a8
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41814
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-24 19:29:29 +00:00
Tiago Mück
fcc55955e2 mem-ruby: removed Message copy constructors
Prevents error with deprecated implicitly-declared operator= when
Message assignment operator is used.

The copy constructor in the Message class and the ones generated from
SLICC are not doing anything special so use the compiler-generated ones
instead.

Change-Id: I0edec4a44cbb7858f07ed2f2f189455994055c33
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41813
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-24 19:29:29 +00:00
Gabe Black
8ee05ddd7c scons: Create a small helper function for disecting a build target path.
This function does about half of the work of the loop which determines
the build root and the list of variants.

Change-Id: I4f44d1e2643244a4be889c677b25b83d41a39b19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40970
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-02-24 06:27:28 +00:00
Gabe Black
69ed25971d scons: Eliminate CXX_V and main_dict_keys in SConstruct.
CXX_V isn't used by anything, and main_dict_keys is unnecessary because
using "in" with the whole main environment (which acts like a dict)
checks against the keys without needing a temporary variable.

Change-Id: Iab07246c00b1969858659043cead1dd657b1707b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40963
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-02-24 06:27:28 +00:00
Gabe Black
dbe295ab95 scons: Remove an extraneous Exit().
This isn't necessary after error() which exits on its own.

Change-Id: Icad08c1badc73fa8f41013cc69d6cc5a96ff8fdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40961
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-02-24 06:27:28 +00:00
Gabe Black
41ccb6099b scons: Use SCons' built in CXXVERSION instead of detecting our own.
It's not guaranteed that every compiler will set CXXVERSION, but both
gcc and clang do, and for any check of CXXVERSION to be meaningful, we
have to first check which compiler we're talking about.

Change-Id: Icd15e12832920fec6fa8634bc0fde16cc48e3f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41596
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-02-24 06:27:28 +00:00
Gabe Black
978bd8759a scons: Enable the clang++ and clang tools.
If these tools aren't enabled and CXX isn't set, scons will look for
generically named compiler aliases like cc and c++. These will generally
work, but if scons knows that the compiler is specifically clang, it
will set the CXXCONFIG variable we can use to do compiler version
checking.

Because scons blindly forces a tool into use if you specify it, we need
to use the FindTool method which will check a list of tools and add the
first one that it actually finds.

Change-Id: Ie6bebb8eab531989575c878bee07189541756d2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41673
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-24 06:27:28 +00:00
Kevin Loughlin
b05731f927 arch-x86: Adds rdtscp flag to cpuid for X86KvmCPU
The rdtscp instruction is supported by gem5, so the X86KvmCPU
cpuid flags should be updated accordingly. Otherwise, KVM
needlessly crashes upon executing rdtscp.

Change-Id: If79017e60cbdf0757e929f07e56dba64322846bb
Signed-off-by: Kevin Loughlin <kevlough@umich.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41633
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-23 15:34:18 +00:00
Giacomo Travaglini
57bdbe3b7d dev-arm: Remove the A9GlobalTimer
This is not used anymore

Change-Id: Ia25921cfe47e7f6b895450031abb740f94dc032d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31937
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-23 09:22:47 +00:00
Gabe Black
4d0b56d679 scons: Check for "make" when using LTO with gcc.
gcc uses "make" to parallelize LTO. If we're using gcc and make isn't
found, we have to use single threaded LTO instead. A warning will let
the user know what's happening and that they might want to correct the
situation.

Technically gcc can use the MAKE environment variable to override the
program it uses, although I assume it still has to be "make" compatible.
Given the fairly low likelihood that someone will need that override and
the fact that scons won't pipe that variable through unless we plumb it
up, we'll just ignore that for now.

Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41773
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-23 07:52:40 +00:00
Peter Yuen
b5962abb3d arch-riscv: FS Linux config file for RISC-V
This file is added to provide a clean starter for RISC-V FS Linux
configuration.

Change-Id: Ifd401761be86758340f26edd00a5ab1ca51e6938
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41033
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-23 03:43:47 +00:00
Peter
69eb60d87e arch-riscv: RISC-V HiFive Platform implementation
This patch implements the RISC-V HiFive Platform
(based on the SiFive HiFive series). The HiFive
platform requires a PLIC and CLINT device (based on
current HiFive boards).

The optional uart_int_id field redirects Console interrupts
to the PLIC interrupt controller.

PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).

VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC

PlicDevice is a wrapper around BasicPioDevice that
requires an interrupt ID. Interrupts are expected to
be raised via platform->postPciInterrupt(id).

VirtIOMMIO is a slight modification from the ARM
implementation such that interrupts are posted through
PLIC.

Uart8250 was modified slightly for easier Python
setup.

Change-Id: I4bbdb5f903b52a41d1b7e0ccc44877c46cd30d56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40599
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-23 03:43:47 +00:00
Peter
de06ab35ef arch-riscv: PLIC Implementation
This patch contains the implementation for the RISC-V PLIC.
The PLIC Memory Map is based on the SiFive U54MC datasheet.
The PLIC models a 3-cycle latency as stated in the RISC-V
specs.

Change-Id: I571c7bd3bd2918c92e4f207a1b57cf9d06e9c72f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40598
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-23 03:43:47 +00:00
Peter
4cca1d89e8 arch-riscv: Implementation of CLINT
This patch implements the CLINT device model based
on the SiFive U54MC datasheet. CLINT is modelled to
receive its clock signal via an interrupt pin. A
generic RTC (non-MMIO) is also implemented to provide
this signal at arbitrary frequencies.

isa.cc is also modified to provide a correct implementation
of the rdtime instruction. It will read from the miscreg
file (which is updated by CLINT every time mtime is
incremented).

Change-Id: I6f5393f3a8fdbd059f25df51d3d74bcb28da09f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40597
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-02-23 03:43:47 +00:00
Peter
061a6bd219 arch-riscv: Added PMA support for RiscvTLB
Since the RISC-V privileged specs V1.11 did not specify
an implementation of physical memory attributes (PMA), e.g.
cacheability, an abstract PMAChecker class is created. This
class acts as a generic PMAChecker hardware without any
latency modelling.

The TLB finds the PMAChecker defined at the MMU level by
Parent.any.

Change-Id: I4400133895be44da67536d80b82422ec3a49d786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40596
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-23 03:43:47 +00:00
Peter
3a0c3aecaf arch-riscv: Fixing interrupt handling order and effect of mideleg
This patch fixes the issues listed in:
https://gem5.atlassian.net/browse/GEM5-887
https://gem5.atlassian.net/browse/GEM5-889

The code change has been verified by booting FS linux.
Software, timer and external interrupts work as expected.

Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40076
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-23 03:43:47 +00:00
Gabe Black
d32c140bde arch,cpu: Move the inUserMode function to the ISA object.
This function is used when tracing execution with --debug-flags=Exec.
The data used by the function (now method) is stored in the ISA object,
and so that's a logical place to move it.

Change-Id: I624f9365124679343e988cabfb4e1929225b439a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39323
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-21 10:19:18 +00:00
Bobby R. Bruce
f69811ad20 base-stats,python: Update PyBind11 ScalarInfo fields to readonly
This change keeps the ScalarInfo class consistent with the other Info
classes exposed via PyBind11.

Change-Id: I4d420d509e4654de844e75f58aeaaf67109775d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41693
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-20 06:27:27 +00:00
Bobby R. Bruce
4dc66b03f1 base-stats,python: Expose FormulaInfo via PyBind11
Change-Id: If7d3e7a386e138d5f4e05bb1ec4b920d6caef836
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39300
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-20 06:27:27 +00:00
Bobby R. Bruce
10cccabd15 base-stats,python: Expose VectorInfo via Pybind11
Change-Id: Iba5fd1dfd1e4c35f01bf4a6fc28481c1be3dd028
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39299
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-20 06:27:27 +00:00
Bobby R. Bruce
45b37b7eff base-stats,python: Expose DistInfo via Pybind11
Change-Id: If3ac9a0da52b929559e3cde3c2bab95b59ab16ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39298
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-20 06:27:27 +00:00
Giacomo Travaglini
41928dac80 misc: Remove unused params() definitions
Lots of times the params() helper has been defined but not used

Change-Id: Id71829aca71341d46964d8f071099342b946b62f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41613
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 23:27:34 +00:00
Alexander Klimov
92ba3ba843 misc: Use PARAMS
The patch is using the newly defined PARAMS macro to replace
custom params() getters in derived class.

The patch is also removing redundant _params:
Instead of creating yet another _params field, SimObject descendants
should use params() to expose the real type of SimObject::_params they
already have.

Change-Id: I43394cebb9661fe747bdbb332236f0f0181b3dba
Signed-off-by: Alexander Klimov <Alexander.Klimov@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39900
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 23:27:34 +00:00
Gabe Black
c8a2114df2 arch: Eliminate the getArgument function.
This ISA switched function is no longer used. Eliminate it, and reduce
the number of functions used in the switched utility.hh header by one.

Change-Id: Ic6020c5fa6d976d9dbf1e9f517809acf9b0b7cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39321
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 22:08:52 +00:00
Daniel R. Carvalho
6c32f9e521 base: Remove hostname from hostinfo
This function is not used anywhere.

In addition, gethostname uses a fixed host name, and
sethostname is not implemented (sim/syscall_emul). If
we were to handle sethostname too it would require a
special conjoint implementation anyway.

Change-Id: I20919a49b123a6a49582d9cfacf1fd167cb44776
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41394
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 16:41:09 +00:00
Daniel R. Carvalho
eb76992dad base: Clean up base/hostinfo
General fixes to the style of base/hostinfo.(cc|hh).

Remove unnecessary includes.

Remove signature of private functions from header.

Add documentation.

Remove unnecessary include in sim_events.cc.

Change-Id: I54e1f13231e512d26cf0127cc80256fb5e91bf91
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41393
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 16:40:22 +00:00
Daniel R. Carvalho
7ca5ed70e6 base: Fix scientific number conversion in base/str
Previously converting scientific numbers to non-floating
numbers would yield incorrect results, because the
underlying conversion was using stoll and stoull, which
do not deal with scientific numbers properly. Therefore,
converting to_number("8.234e+08", val) would yield
val=8, which is blatantly wrong (expected 823400000).

This was fixed by searching for "e" within the string to
be converted.

To make sure all double and scientific number conversions
are correct, a few extra tests were added.

Change-Id: I6a9599d8473909d274326b6f8c268e3603044ab4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38775
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 16:39:35 +00:00