arch-riscv: Added PMA support for RiscvTLB

Since the RISC-V privileged specs V1.11 did not specify
an implementation of physical memory attributes (PMA), e.g.
cacheability, an abstract PMAChecker class is created. This
class acts as a generic PMAChecker hardware without any
latency modelling.

The TLB finds the PMAChecker defined at the MMU level by
Parent.any.

Change-Id: I4400133895be44da67536d80b82422ec3a49d786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40596
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/PMAChecker.py

@@ -0,0 +1,45 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+class PMAChecker(SimObject):
+    type = 'PMAChecker'
+    cxx_header = 'arch/riscv/pma_checker.hh'
+    uncacheable = VectorParam.AddrRange([], "Uncacheable address ranges")

src/arch/riscv/RiscvMMU.py

@@ -37,6 +37,7 @@
 
 from m5.objects.BaseMMU import BaseMMU
 from m5.objects.RiscvTLB import RiscvTLB
+from m5.objects.PMAChecker import PMAChecker
 
 class RiscvMMU(BaseMMU):
     type = 'RiscvMMU'
@@ -44,6 +45,7 @@ class RiscvMMU(BaseMMU):
     cxx_header = 'arch/riscv/mmu.hh'
     itb = RiscvTLB()
     dtb = RiscvTLB()
+    pma_checker = PMAChecker()
 
     @classmethod
     def walkerPorts(cls):

src/arch/riscv/RiscvTLB.py

@@ -2,6 +2,7 @@
 
 # Copyright (c) 2007 MIPS Technologies, Inc.
 # Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -41,6 +42,8 @@ class RiscvPagetableWalker(ClockedObject):
     system = Param.System(Parent.any, "system object")
     num_squash_per_cycle = Param.Unsigned(4,
             "Number of outstanding walks that can be squashed per cycle")
+    # Grab the pma_checker from the MMU
+    pma_checker = Param.PMAChecker(Parent.any, "PMA Chekcer")
 
 class RiscvTLB(BaseTLB):
     type = 'RiscvTLB'
@@ -49,3 +52,5 @@ class RiscvTLB(BaseTLB):
     size = Param.Int(64, "TLB size")
     walker = Param.RiscvPagetableWalker(\
             RiscvPagetableWalker(), "page table walker")
+    # Grab the pma_checker from the MMU
+    pma_checker = Param.PMAChecker(Parent.any, "PMA Chekcer")

src/arch/riscv/SConscript

@@ -51,6 +51,7 @@ if env['TARGET_ISA'] == 'riscv':
     Source('process.cc')
     Source('pagetable.cc')
     Source('pagetable_walker.cc')
+    Source('pma_checker.cc')
     Source('reg_abi.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
@@ -60,6 +61,7 @@ if env['TARGET_ISA'] == 'riscv':
 
     Source('bare_metal/fs_workload.cc')
 
+    SimObject('PMAChecker.py')
     SimObject('RiscvFsWorkload.py')
     SimObject('RiscvInterrupts.py')
     SimObject('RiscvISA.py')

src/arch/riscv/pagetable_walker.cc

@@ -489,6 +489,7 @@ Walker::WalkerState::recvPacket(PacketPtr pkt)
             vaddr &= (static_cast<Addr>(1) << VADDR_BITS) - 1;
             Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid, mode);
             req->setPaddr(paddr);
+            walker->pma->check(req);
             // Let the CPU continue.
             translation->finish(NoFault, req, tc, mode);
         } else {

src/arch/riscv/pagetable_walker.hh

@@ -42,6 +42,7 @@
 #include <vector>
 
 #include "arch/riscv/pagetable.hh"
+#include "arch/riscv/pma_checker.hh"
 #include "arch/riscv/tlb.hh"
 #include "base/types.hh"
 #include "mem/packet.hh"
@@ -166,6 +167,7 @@ namespace RiscvISA
         // The TLB we're supposed to load.
         TLB * tlb;
         System * sys;
+        PMAChecker * pma;
         RequestorID requestorId;
 
         // The number of outstanding walks that can be squashed per cycle.
@@ -196,6 +198,7 @@ namespace RiscvISA
         Walker(const Params &params) :
             ClockedObject(params), port(name() + ".port", this),
             funcState(this, NULL, NULL, true), tlb(NULL), sys(params.system),
+            pma(params.pma_checker),
             requestorId(sys->getRequestorId(this)),
             numSquashable(params.num_squash_per_cycle),
             startWalkWrapperEvent([this]{ startWalkWrapper(); }, name())

src/arch/riscv/pma_checker.cc

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/riscv/pma_checker.hh"
+
+#include "base/addr_range.hh"
+#include "base/types.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "params/PMAChecker.hh"
+#include "sim/sim_object.hh"
+
+PMAChecker::PMAChecker(const Params &params) :
+SimObject(params),
+uncacheable(params.uncacheable.begin(), params.uncacheable.end())
+{
+}
+
+void
+PMAChecker::check(const RequestPtr &req)
+{
+    if (isUncacheable(req->getPaddr(), req->getSize())) {
+        req->setFlags(Request::UNCACHEABLE);
+    }
+}
+
+bool
+PMAChecker::isUncacheable(const AddrRange &range)
+{
+    for (auto const &uncacheable_range: uncacheable) {
+        if (range.isSubset(uncacheable_range)) {
+            return true;
+        }
+    }
+    return false;
+}
+
+bool
+PMAChecker::isUncacheable(const Addr &addr, const unsigned size)
+{
+    AddrRange range(addr, addr + size);
+    return isUncacheable(range);
+}
+
+bool
+PMAChecker::isUncacheable(PacketPtr pkt)
+{
+    return isUncacheable(pkt->getAddrRange());
+}

src/arch/riscv/pma_checker.hh

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_PMA_CHECKER_HH__
+#define __ARCH_RISCV_PMA_CHECKER_HH__
+
+#include "base/addr_range.hh"
+#include "base/types.hh"
+#include "mem/packet.hh"
+#include "params/PMAChecker.hh"
+#include "sim/sim_object.hh"
+
+/**
+ * Based on the RISC-V ISA privileged specifications
+ * V1.11, there is no implementation guidelines on the
+ * Physical Memory Attributes.
+ *
+ * This class provides an abstract PMAChecker for RISC-V
+ * to provide PMA checking functionality. However,
+ * hardware latencies are not modelled.
+ */
+
+class PMAChecker : public SimObject
+{
+  public:
+
+    typedef PMACheckerParams Params;
+
+    const Params &
+    params() const
+    {
+        return dynamic_cast<const Params &>(_params);
+    }
+    PMAChecker(const Params &params);
+
+    AddrRangeList uncacheable;
+
+    void check(const RequestPtr &req);
+
+    bool isUncacheable(const AddrRange &range);
+    bool isUncacheable(const Addr &addr, const unsigned size);
+    bool isUncacheable(PacketPtr pkt);
+};
+
+#endif // __ARCH_RISCV_PMA_CHECKER_HH__

src/arch/riscv/tlb.cc

@@ -2,6 +2,7 @@
  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * Copyright (c) 2020 Barkhausen Institut
+ * Copyright (c) 2021 Huawei International
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -38,6 +39,7 @@
 #include "arch/riscv/mmu.hh"
 #include "arch/riscv/pagetable.hh"
 #include "arch/riscv/pagetable_walker.hh"
+#include "arch/riscv/pma_checker.hh"
 #include "arch/riscv/pra_constants.hh"
 #include "arch/riscv/utility.hh"
 #include "base/inifile.hh"
@@ -65,8 +67,9 @@ buildKey(Addr vpn, uint16_t asid)
     return (static_cast<Addr>(asid) << 48) | vpn;
 }
 
-TLB::TLB(const Params &p)
-    : BaseTLB(p), size(p.size), tlb(size), lruSeq(0), stats(this)
+TLB::TLB(const Params &p) :
+    BaseTLB(p), size(p.size), tlb(size),
+    lruSeq(0), stats(this), pma(p.pma_checker)
 {
     for (size_t x = 0; x < size; x++) {
         tlb[x].trieHandle = NULL;
@@ -361,6 +364,10 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc,
             fault = std::make_shared<AddressFault>(req->getVaddr(), code);
         }
 
+        if (!delayed && fault == NoFault) {
+            pma->check(req);
+        }
+
         return fault;
     } else {
         // In the O3 CPU model, sometimes a memory access will be speculatively

src/arch/riscv/tlb.hh

@@ -2,6 +2,7 @@
  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * Copyright (c) 2020 Barkhausen Institut
+ * Copyright (c) 2021 Huawei International
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,6 +38,7 @@
 #include "arch/riscv/isa.hh"
 #include "arch/riscv/isa_traits.hh"
 #include "arch/riscv/pagetable.hh"
+#include "arch/riscv/pma_checker.hh"
 #include "arch/riscv/utility.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
@@ -81,6 +83,9 @@ class TLB : public BaseTLB
         Stats::Formula accesses;
     } stats;
 
+  public:
+    PMAChecker *pma;
+
   public:
     typedef RiscvTLBParams Params;
     TLB(const Params &p);