arch-riscv: FS Linux config file for RISC-V
This file is added to provide a clean starter for RISC-V FS Linux configuration. Change-Id: Ifd401761be86758340f26edd00a5ab1ca51e6938 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41033 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Peter Yuen
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configs/example/riscv/fs_linux.py
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configs/example/riscv/fs_linux.py
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# Copyright (c) 2021 Huawei International
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
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# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import optparse
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath, fatal, warn
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from m5.util.fdthelper import *
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addToPath('../../')
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from ruby import Ruby
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from common.FSConfig import *
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from common.SysPaths import *
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from common.Benchmarks import *
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from common import Simulation
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from common import CacheConfig
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from common import CpuConfig
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from common import MemConfig
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from common import ObjectList
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from common.Caches import *
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from common import Options
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# ----------------------------- Add Options ---------------------------- #
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# NOTE: Ruby in FS Linux has not been tested yet
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if '--ruby' in sys.argv:
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Ruby.define_options(parser)
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# ---------------------------- Parse Options --------------------------- #
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(options, args) = parser.parse_args()
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if args:
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print("Error: script doesn't take any positional arguments")
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sys.exit(1)
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# CPU and Memory
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(CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(options)
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MemClass = Simulation.setMemClass(options)
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np = options.num_cpus
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# ---------------------------- Setup System ---------------------------- #
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# Edit this section to customize peripherals and system settings
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system = System()
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mdesc = SysConfig(disks=options.disk_image, rootdev=options.root_device,
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mem=options.mem_size, os_type=options.os_type)
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system.mem_mode = mem_mode
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system.mem_ranges = [AddrRange(start=0x80000000, size=mdesc.mem())]
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system.workload = RiscvBareMetal()
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system.iobus = IOXBar()
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system.membus = MemBus()
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system.system_port = system.membus.slave
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system.intrctrl = IntrControl()
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# HiFive platform
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system.platform = HiFive()
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# RTCCLK (Set to 100MHz for faster simulation)
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system.platform.rtc = RiscvRTC(frequency=Frequency("100MHz"))
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system.platform.clint.int_pin = system.platform.rtc.int_pin
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# VirtIOMMIO
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image = CowDiskImage(child=RawDiskImage(read_only=True), read_only=False)
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image.child.image_file = mdesc.disks()[0]
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system.platform.disk = MmioVirtIO(
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vio=VirtIOBlock(image=image),
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interrupt_id=0x8,
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pio_size=4096,
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pio_addr=0x10008000
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)
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system.bridge = Bridge(delay='50ns')
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system.bridge.mem_side_port = system.iobus.cpu_side_ports
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system.bridge.cpu_side_port = system.membus.mem_side_ports
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system.bridge.ranges = system.platform._off_chip_ranges()
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system.platform.attachOnChipIO(system.membus)
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system.platform.attachOffChipIO(system.iobus)
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system.platform.attachPlic()
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# ---------------------------- Default Setup --------------------------- #
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# Set the cache line size for the entire system
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system.cache_line_size = options.cacheline_size
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# Create a top-level voltage domain
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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# Create a source clock for the system and set the clock period
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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# Create a CPU voltage domain
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system.cpu_voltage_domain = VoltageDomain()
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# Create a source clock for the CPUs and set the clock period
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system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
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voltage_domain =
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system.cpu_voltage_domain)
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system.workload.bootloader = options.kernel
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# NOTE: Not yet tested
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if options.script is not None:
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system.readfile = options.script
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system.init_param = options.init_param
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system.cpu = [CPUClass(clk_domain=system.cpu_clk_domain, cpu_id=i)
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for i in range(np)]
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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system.iocache = IOCache(addr_ranges = system.mem_ranges)
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system.iocache.cpu_side = system.iobus.master
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system.iocache.mem_side = system.membus.slave
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elif not options.external_memory_system:
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system.iobridge = Bridge(delay='50ns', ranges = system.mem_ranges)
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system.iobridge.slave = system.iobus.master
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system.iobridge.master = system.membus.slave
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# Sanity check
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if options.simpoint_profile:
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if not ObjectList.is_noncaching_cpu(CPUClass):
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fatal("SimPoint generation should be done with atomic cpu")
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if np > 1:
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fatal("SimPoint generation not supported with more than one CPUs")
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for i in range(np):
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if options.simpoint_profile:
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system.cpu[i].addSimPointProbe(options.simpoint_interval)
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if options.checker:
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system.cpu[i].addCheckerCpu()
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if not ObjectList.is_kvm_cpu(CPUClass):
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if options.bp_type:
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bpClass = ObjectList.bp_list.get(options.bp_type)
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system.cpu[i].branchPred = bpClass()
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if options.indirect_bp_type:
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IndirectBPClass = ObjectList.indirect_bp_list.get(
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options.indirect_bp_type)
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system.cpu[i].branchPred.indirectBranchPred = \
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IndirectBPClass()
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system.cpu[i].createThreads()
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# ----------------------------- PMA Checker ---------------------------- #
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uncacheable_range = [
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*system.platform._on_chip_ranges(),
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*system.platform._off_chip_ranges()
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]
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pma_checker = PMAChecker(uncacheable=uncacheable_range)
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# PMA checker can be defined at system-level (system.pma_checker)
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# or MMU-level (system.cpu[0].mmu.pma_checker). It will be resolved
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# by RiscvTLB's Parent.any proxy
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for cpu in system.cpu:
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cpu.mmu.pma_checker = pma_checker
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# ---------------------------- Default Setup --------------------------- #
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if options.elastic_trace_en and options.checkpoint_restore == None and \
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not options.fast_forward:
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CpuConfig.config_etrace(CPUClass, system.cpu, options)
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CacheConfig.config_cache(options, system)
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MemConfig.config_mem(options, system)
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root = Root(full_system=True, system=system)
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Simulation.setWorkCountOptions(system, options)
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Simulation.run(options, root, system, FutureClass)
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