derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

mem-ruby: renamed prefetch stats

Browse Source 
Splitting hw_prefetches into prefetch_hits and prefetch_misses so both
events can be tracked separately. Also added appropriate functions to
increment stats. Renamed m_prefetches for consistency.

sw_prefetches is not used and has been removed. The sequencer converts
SW prefetch requests into a RubyRequestType_LD/RubyRequestType_ST
which are handled as demand requests by the all current protocols.

Change-Id: Iafa6b31c84843ddd1fad98fa7e5afed02b8c4b4d
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41816
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2020-10-01 18:18:23 -05:00
parent 1a9716044a
commit 5b9517f196
3 changed files with 29 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mem/ruby/protocol/RubySlicc_Types.sm
View File

@@ -215,6 +215,8 @@ structure (CacheMemory, external = "yes") {
void profileDemandHit();
void profileDemandMiss();
void profilePrefetchHit();
void profilePrefetchMiss();
}
structure (WireBuffer, inport="yes", outport="yes", external = "yes") {

29
src/mem/ruby/structures/CacheMemory.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 ARM Limited
* Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -533,10 +533,10 @@ CacheMemoryStats::CacheMemoryStats(Stats::Group *parent)
ADD_STAT(m_demand_misses, "Number of cache demand misses"),
ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
m_demand_hits + m_demand_misses),
ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
ADD_STAT(m_prefetches, "Number of prefetches",
m_sw_prefetches + m_hw_prefetches),
ADD_STAT(m_prefetch_hits, "Number of cache prefetch hits"),
ADD_STAT(m_prefetch_misses, "Number of cache prefetch misses"),
ADD_STAT(m_prefetch_accesses, "Number of cache prefetch accesses",
m_prefetch_hits + m_prefetch_misses),
ADD_STAT(m_accessModeType, "")
{
numDataArrayReads
@@ -573,13 +573,13 @@ CacheMemoryStats::CacheMemoryStats(Stats::Group *parent)
.init(8)
.flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan);
m_sw_prefetches
m_prefetch_hits
.flags(Stats::nozero);
m_hw_prefetches
m_prefetch_misses
.flags(Stats::nozero);
m_prefetches
m_prefetch_accesses
.flags(Stats::nozero);
m_accessModeType
@@ -747,3 +747,16 @@ CacheMemory::profileDemandMiss()
{
cacheMemoryStats.m_demand_misses++;
}
void
CacheMemory::profilePrefetchHit()
{
cacheMemoryStats.m_prefetch_hits++;
}
void
CacheMemory::profilePrefetchMiss()
{
cacheMemoryStats.m_prefetch_misses++;
}

10
src/mem/ruby/structures/CacheMemory.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 ARM Limited
* Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -228,9 +228,9 @@ class CacheMemory : public SimObject
Stats::Scalar m_demand_misses;
Stats::Formula m_demand_accesses;
Stats::Scalar m_sw_prefetches;
Stats::Scalar m_hw_prefetches;
Stats::Formula m_prefetches;
Stats::Scalar m_prefetch_hits;
Stats::Scalar m_prefetch_misses;
Stats::Formula m_prefetch_accesses;
Stats::Vector m_accessModeType;
} cacheMemoryStats;
@@ -240,6 +240,8 @@ class CacheMemory : public SimObject
// each time they are called
void profileDemandHit();
void profileDemandMiss();
void profilePrefetchHit();
void profilePrefetchMiss();
};
std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);