arch-arm: Fix atomics permission checks in TLB

For stage 2 translations, atomic accesses were not checking the
access permission bits in the page table descriptors, and were
instead wrongly using the nature of the request itself
(r/w booleans).

Change-Id: I27fbc95f04ea659e77ad5a3afb551873c9c971f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42073
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/tlb.cc

@@ -872,8 +872,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
             // sctlr.wxn overrides the xn bit
             grant = !wxn && !xn;
         } else if (is_atomic) {
-            grant = r && w;
-            grant_read = r;
+            grant = hap;
         } else if (is_write) {
             grant = hap & 0x2;
         } else { // is_read