Don't use the "E" tag when there is only a register or memory based
version of the instruction, since that decodes to both. Don't special
case the "st(1)" version of an instruction if it's just a matter of the
assembly syntax and not the instruction encoding. Don't decode based on
Mod, and then use the tag type "E" which will again decode on Mod, use
"E" for both the memory and register versions at the same time. Set the
default instruction to Inst::UD2 so that we don't have to specify it as
the default locally in each decode block. Let the "M" tag handle the Mod
= 3 case, which is built into that operand type. That's slightly
inconsistent with the "R" type which does not handle the "not 3" case,
but we can take advantage of it none the less.
There are instructions which, when decoded as the Inst format, will take
the "M" type tag and be able to drop their decoding of the Mod = 3 case,
but since they aren't Inst right now and can't sub-decode Mod on their
own, the 3 case needs to stay for now.
In most cases when dealing with x87 registers, the "dataSize" argument
to microops doesn't matter since the size doesn't change. There may be
an opportunity to consolidate the various FP microops and use dataSize
= 10 for x87 registers, although there are some nuances there that may
make that not work out.
Change-Id: Ia3ff6176796af66f6a3c463b538e750e65893a84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42904
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
This unused pair of methods could be used to trigger a breakpoint within
the remote GDB stub, but was unused and would need to be called from an
instance of GDB attached to gem5 itself.
The system's version of breakpoint was also limitted in that it would
only cause a breakpoint in the first thread's GDB and no other.
Change-Id: I53ceab78667610177dbb8be1def3a88262befeec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44031
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit removes functions that indexed into the
vectors that held the operands. Instead, for-each loops
are used, iterating through one of 6 vectors
(src, dst, srcScalar, srcVec, dstScalar, dstVec)
that all hold various (potentially overlapping)
combinations of the operands.
Change-Id: Ia3a857c8f6675be86c51ba2f77e3d85bfea9ffdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42212
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This change removes the GPUDynInstPtr argument from
getRegisterIndex(). The dynamic inst was only needed
to get access to its parent WF's state so it could
determine the number of scalar registers the wave was
allocated. However, we can simply pass the number of
scalar registers directly. This cuts down on shared
pointer usage.
Change-Id: I29ab8d9a3de1f8b82b820ef421fc653284567c65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42210
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
The unnecessary DependenceTags is already being removed by another
pending change, and so is left in place for that to remove. Once that's
happened, the regs/*.hh includes can be removed, and there may be other
include related tangles to sort out.
Change-Id: I1c02aa8fd2f2045017609b70523b3519c2a92b03
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41742
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The SouthBridge used to have a parameter to point back at a Platform
object which it would dynamically cast to the Pc platform type, and it
would use that to tell the Pc platform where it was. The Pc platform
would then configure initial values in the SouthBridge during the init
phase. Now, the Pc platform has a parameter which by default
instantiates a SouthBridge, so that it will have a pointer
automatically. The Pc object knows it will have a SouthBridge, and now
the SouthBridge no longer has to assume that it's housed inside a Pc
platform.
Also, the SouthBridge device had instantiated a lot of child objects,
and then to ensure that they were accessible in c++, they were also set
as parameters on the object. Now, these children are created as the
default value for those parameters. They no longer have to be declared
and then separately hooked up as parameters. They could also
theoretically be replaced more easily since they're now only defaults,
although in practice that's unlikely.
Change-Id: I296b18a55ab6aedbb609ca4f545f7b19c21fd905
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43886
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This class, because it inherits from AddrMapper, would only poke its
upstream port to let it know to request its address range if it's
downstream port had asked it to. This doesn't make sense, since the
RangeAddrMapper has a fixed range it will respond to. Also, when the
RangeAddrMapper is notified that it's downstream port has an updated
range, the mapper should request that range and make sure all of the
addresses it will output are in the range the other object expects.
Change-Id: I57b558644b103822a9af53733bdb8518836ef5de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43346
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This utility receives input from stdin or a file, buffers up to "n"
lines of it, and prints those lines either when it reaches the end of
the file/stdin, or when it receives a SIGUSR1 which can be sent to it
using the "kill" utility. When it receives a SIGUSR1, it keeps running
and tracking the input.
Change-Id: I9eca4514378cf24a31002d37e10e58cc3ee63b5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43266
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Add the file .git-blame-ignore-revs to store the hash
of the commits that should be ignored on a git blame.
The commit hash should be added after the commit has
been merged. New hashes should be added as the first
line of the file.
Add some initial contents with commits that only fix
the style.
Usage example:
git blame file.py --ignore-revs-file .git-blame-ignore-revs
To always ignore from this file on git blames:
git config blame.ignoreRevsFile .git-blame-ignore-revs
Change-Id: Idd29cb933d4157f1650658acc7efc1bd142fa7c7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43594
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The only thing left in isa_traits.hh are two constants, one for the
number of bytes in a page, and one for how far to shift an address to
get the page number. To make it clear that this is the only thing
isa_traits.hh should be used for from this point forward (until it is
entirely eliminated), this change renames it to the much less generic
page_size.hh.
Also, because isa_traits.hh used to have *much* more stuff in it, it was
included in a lot of places it didn't need to be. This change also
clears out all these legacy includes while updating the actually needed
ones to the new name.
Change-Id: I939b01b117c53d620b6b0a98982f6f21dc2ada72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40179
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The default behavior already is to add color to the output. The option
had an action of 'store_true' which would normally set the default value
to False, but the --no-colors option immediately after it had the action
'store_false' which apparently set the common dest 'use_colors' to True
by default. The net effect was that the --colors option did nothing.
Change-Id: I6d6473f85921f90bb629ecb32a0f0f81c02d7914
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40875
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
The BUILD_GPU setting was being set by adding a -D to the command line
at the top level SConstruct. Instead, add BUILD_GPU to export_vars so
that it ends up in a config/build_gpu.hh header. Also switch it from the
fairly dangerous #ifdef style to the safer #if.
Change-Id: Ic93d37c9d7671023a6978842dbb2750c3e92f8d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40873
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.
Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
dGPUs in all versions of ROCm and APUs starting with ROCM 2.2 can
under-allocate scratch resources. This patch adds support for
the CP to trigger a recoverable error so that the host can attempt to
re-allocate scratch to satisfy the currently stalled kernel.
Note that this patch does not include a mechanism to handle dynamic
scratch allocation for queues with in-flight kernels, as these queues
would first need to be drained and descheduled, which would require some
additional effort in the hsaPP and HW queue scheduler. If the CP
encounters this scenerio it will assert. I suspect this is not a
particularly common occurence in most of our applications so it is left
as a TODO.
This patch also fixes a few memory leaks and updates the old DMA callback
object interface to use a much cleaner c++11 lambda interface.
Change-Id: Ica8a5fc88888283415507544d6cc49fa748fe84d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42201
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
In the HSAQueueDescriptor ptr function, we mod the index by numElts, but
numElts was previously just set to size, which was the raw size of the
queue. This lead to indexing past the queue. We fix this by dividing by
the size by the AQL packet size to get the actual number of elements the
queue can hold.
We also add an assert for indexing into the queue, as there is a
scenario where the queue reports a larger size than it actually is.
Change-Id: Ie5e699379f303255305c279e58a34dc783df86a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42423
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This patch is adding an extra parameter to the Ruby.create_system
function. The idea is to remove any assumption about cpu configuration
in the ruby scripts.
At the moment the scripts are assuming a flat list of cpu assigned
to the system object. Unfortunately this is not standardized, as
some systems might empoloy a different layout of cpus, like grouping
them in cluster objects.
With this patch we are allowing client scripts to provide the cpu list
as an extra argument
This has the extra benefit of removing the indexing hack
if len(system.cpu) == 1:
which was present in most scripts
Change-Id: Ibc06b920273cde4f7c394d61c0ca664a7143cd27
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43287
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
