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arch-vega: Update FLAT instructions to use offset

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In Vega, flat instructions use an offset when
computing the address (section 9.4 of chapter 9
'Flat Memory Instructions' in Vega ISA manual).
This is different from the GCN3 baseline.

Change-Id: I9fe36f028014889ef566055458c451442403a289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42213
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Kyle Roarty
2019-07-25 13:36:00 -04:00
committed by Matt Sinclair
parent 2bb8d6bc0c
commit 49f7565904
2 changed files with 20 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
src/arch/amdgpu/vega/insts/instructions.cc
View File

@@ -42461,7 +42461,7 @@ namespace VegaISA
addr.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe
@@ -42552,7 +42552,7 @@ namespace VegaISA
addr.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe
@@ -42644,7 +42644,7 @@ namespace VegaISA
addr.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe
@@ -42707,7 +42707,7 @@ namespace VegaISA
addr.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe
@@ -42770,7 +42770,7 @@ namespace VegaISA
addr.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe
@@ -42841,7 +42841,7 @@ namespace VegaISA
addr.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe
@@ -42920,7 +42920,7 @@ namespace VegaISA
data.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -42983,7 +42983,7 @@ namespace VegaISA
addr.read();
data.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -43046,7 +43046,7 @@ namespace VegaISA
addr.read();
data.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -43117,7 +43117,7 @@ namespace VegaISA
}
}
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe
@@ -43178,7 +43178,7 @@ namespace VegaISA
data1.read();
data2.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -43252,7 +43252,7 @@ namespace VegaISA
data2.read();
data3.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -43329,7 +43329,7 @@ namespace VegaISA
addr.read();
data.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -43417,7 +43417,7 @@ namespace VegaISA
data.read();
cmp.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -43501,7 +43501,7 @@ namespace VegaISA
addr.read();
data.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
(reinterpret_cast<VecElemU32*>(gpuDynInst->a_data))[lane]
@@ -43894,7 +43894,7 @@ namespace VegaISA
}
}
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
if (isFlatGlobal()) {
gpuDynInst->computeUnit()->globalMemoryPipe.
@@ -43970,7 +43970,7 @@ namespace VegaISA
addr.read();
data.read();
calcAddr(gpuDynInst, addr);
calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {

5
src/arch/amdgpu/vega/insts/op_encodings.hh
View File

@@ -789,11 +789,12 @@ namespace VegaISA
}
void
calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr)
calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr,
ScalarRegU32 offset)
{
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
gpuDynInst->addr.at(lane) = addr[lane];
gpuDynInst->addr.at(lane) = addr[lane] + offset;
}
}
gpuDynInst->resolveFlatSegment(gpuDynInst->exec_mask);