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arch-vega: Update instruction encodings

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This also renames VOP3 and VOP3_SDST_ENC to
VOP3A and VOP3B, matching the ISA.

Change-Id: I56f254433b1f3181d4ee6896f957a2256e3c7b29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42205
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Kyle Roarty
2019-06-27 14:03:49 -04:00
committed by Matt Sinclair
parent f7d4ff6ef5
commit b30e9645d7
7 changed files with 2111 additions and 2063 deletions
Download Patch File Download Diff File Expand all files Collapse all files

798
src/arch/amdgpu/vega/decoder.cc
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File diff suppressed because it is too large Load Diff

85
src/arch/amdgpu/vega/gpu_decoder.hh
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@@ -1390,7 +1390,9 @@ namespace VegaISA
};
struct InFmt_FLAT {
unsigned int pad_0_15 : 16;
unsigned int OFFSET : 13;
unsigned int LDS : 1;
unsigned int SEG : 2;
unsigned int GLC : 1;
unsigned int SLC : 1;
unsigned int OP : 7;
@@ -1401,8 +1403,8 @@ namespace VegaISA
struct InFmt_FLAT_1 {
unsigned int ADDR : 8;
unsigned int DATA : 8;
unsigned int pad_16_22 : 7;
unsigned int TFE : 1;
unsigned int SADDR : 7;
unsigned int NV : 1;
unsigned int VDST : 8;
};
@@ -1411,12 +1413,13 @@ namespace VegaISA
};
struct InFmt_MIMG {
unsigned int pad_0_7 : 8;
unsigned int OPM : 1;
unsigned int pad_1_7 : 7;
unsigned int DMASK : 4;
unsigned int UNORM : 1;
unsigned int UNRM : 1;
unsigned int GLC : 1;
unsigned int DA : 1;
unsigned int R128 : 1;
unsigned int A16 : 1;
unsigned int TFE : 1;
unsigned int LWE : 1;
unsigned int OP : 7;
@@ -1479,7 +1482,9 @@ namespace VegaISA
struct InFmt_SMEM {
unsigned int SBASE : 6;
unsigned int SDATA : 7;
unsigned int pad_13_15 : 3;
unsigned int pad_13 : 1;
unsigned int SOE : 1;
unsigned int NV : 1;
unsigned int GLC : 1;
unsigned int IMM : 1;
unsigned int OP : 8;
@@ -1487,7 +1492,9 @@ namespace VegaISA
};
struct InFmt_SMEM_1 {
unsigned int OFFSET : 20;
unsigned int OFFSET : 21;
unsigned int pad_21_24 : 4;
unsigned int SOFFSET : 7;
};
struct InFmt_SOP1 {
@@ -1549,10 +1556,10 @@ namespace VegaISA
unsigned int ENCODING : 1;
};
struct InFmt_VOP3 {
struct InFmt_VOP3A {
unsigned int VDST : 8;
unsigned int ABS : 3;
unsigned int pad_11_14 : 4;
unsigned int OPSEL : 4;
unsigned int CLAMP : 1;
unsigned int OP : 10;
unsigned int ENCODING : 6;
@@ -1566,7 +1573,7 @@ namespace VegaISA
unsigned int NEG : 3;
};
struct InFmt_VOP3_SDST_ENC {
struct InFmt_VOP3B {
unsigned int VDST : 8;
unsigned int SDST : 7;
unsigned int CLAMP : 1;
@@ -1585,7 +1592,7 @@ namespace VegaISA
unsigned int SRC0 : 8;
unsigned int DPP_CTRL : 9;
unsigned int pad_17_18 : 2;
unsigned int BOUND_CTRL : 1;
unsigned int BC : 1;
unsigned int SRC0_NEG : 1;
unsigned int SRC0_ABS : 1;
unsigned int SRC1_NEG : 1;
@@ -1597,18 +1604,57 @@ namespace VegaISA
struct InFmt_VOP_SDWA {
unsigned int SRC0 : 8;
unsigned int DST_SEL : 3;
unsigned int DST_UNUSED : 2;
unsigned int CLAMP : 1;
unsigned int pad_14_15 : 2;
unsigned int DST_U : 2;
unsigned int CLMP : 1;
unsigned int OMOD : 2;
unsigned int SRC0_SEL : 3;
unsigned int SRC0_SEXT : 1;
unsigned int SRC0_NEG : 1;
unsigned int SRC0_ABS : 1;
unsigned int pad_22_23 : 2;
unsigned int pad_22 : 1;
unsigned int S0 : 1;
unsigned int SRC1_SEL : 3;
unsigned int SRC1_SEXT : 1;
unsigned int SRC1_NEG : 1;
unsigned int SRC1_ABS : 1;
unsigned int pad_30 : 1;
unsigned int S1 : 1;
};
struct InFmt_VOP_SDWAB {
unsigned int SRC0 : 8;
unsigned int SDST : 7;
unsigned int SD : 1;
unsigned int SRC0_SEL : 3;
unsigned int SRC0_SEXT : 1;
unsigned int SRC0_NEG : 1;
unsigned int SRC0_ABS : 1;
unsigned int pad_22 : 1;
unsigned int S0 : 1;
unsigned int SRC1_SEL : 3;
unsigned int SRC1_SEXT : 1;
unsigned int SRC1_NEG : 1;
unsigned int SRC1_ABS : 1;
unsigned int pad_30 : 1;
unsigned int S1 : 1;
};
struct InFmt_VOP3P {
unsigned int VDST : 8;
unsigned int NEG_HI : 3;
unsigned int OPSEL : 3;
unsigned int OPSEL_HI2 : 1;
unsigned int CLMP : 1;
unsigned int OP : 7;
unsigned int ENCODING : 9;
};
struct InFmt_VOP3P_1 {
unsigned int SRC0 : 9;
unsigned int SRC1 : 9;
unsigned int SRC2 : 9;
unsigned int OPSEL_HI : 2;
unsigned int NEG : 3;
};
union InstFormat {
@@ -1635,12 +1681,15 @@ namespace VegaISA
InFmt_VINTRP iFmt_VINTRP;
InFmt_VOP1 iFmt_VOP1;
InFmt_VOP2 iFmt_VOP2;
InFmt_VOP3 iFmt_VOP3;
InFmt_VOP3A iFmt_VOP3A;
InFmt_VOP3_1 iFmt_VOP3_1;
InFmt_VOP3_SDST_ENC iFmt_VOP3_SDST_ENC;
InFmt_VOP3B iFmt_VOP3B;
InFmt_VOPC iFmt_VOPC;
InFmt_VOP_DPP iFmt_VOP_DPP;
InFmt_VOP_SDWA iFmt_VOP_SDWA;
InFmt_VOP_SDWAB iFmt_VOP_SDWAB;
InFmt_VOP3P iFmt_VOP3P;
InFmt_VOP3P_1 iFmt_VOP3P_1;
uint32_t imm_u32;
float imm_f32;
}; // union InstFormat

6
src/arch/amdgpu/vega/insts/inst_util.hh
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@@ -416,7 +416,7 @@ namespace VegaISA
{
// local variables
SqDPPVals dppCtrl = (SqDPPVals)dppInst.DPP_CTRL;
int boundCtrl = dppInst.BOUND_CTRL;
int boundCtrl = dppInst.BC;
int bankMask = dppInst.BANK_MASK;
int rowMask = dppInst.ROW_MASK;
// row, bank info to be calculated per lane
@@ -879,9 +879,9 @@ namespace VegaISA
{
// local variables
const SDWADstVals dst_unusedBits_format =
(SDWADstVals)sdwaInst.DST_UNUSED;
(SDWADstVals)sdwaInst.DST_U;
const SDWASelVals dst_sel = (SDWASelVals)sdwaInst.DST_SEL;
const bool clamp = sdwaInst.CLAMP;
const bool clamp = sdwaInst.CLMP;
/**
* STEP 1: select the appropriate bits for dst and pad/sign-extend as

1628
src/arch/amdgpu/vega/insts/instructions.cc
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File diff suppressed because it is too large Load Diff

1592
src/arch/amdgpu/vega/insts/instructions.hh
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File diff suppressed because it is too large Load Diff

41
src/arch/amdgpu/vega/insts/op_encodings.cc
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@@ -1190,9 +1190,9 @@ namespace VegaISA
return 4;
} // instSize
// --- Inst_VOP3 base class methods ---
// --- Inst_VOP3A base class methods ---
Inst_VOP3::Inst_VOP3(InFmt_VOP3 *iFmt, const std::string &opcode,
Inst_VOP3A::Inst_VOP3A(InFmt_VOP3A *iFmt, const std::string &opcode,
bool sgpr_dst)
: VEGAGPUStaticInst(opcode), sgprDst(sgpr_dst)
{
@@ -1201,20 +1201,20 @@ namespace VegaISA
// copy second instruction DWORD
extData = ((InFmt_VOP3_1 *)iFmt)[1];
_srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
} // Inst_VOP3
} // Inst_VOP3A
Inst_VOP3::~Inst_VOP3()
Inst_VOP3A::~Inst_VOP3A()
{
} // ~Inst_VOP3
} // ~Inst_VOP3A
int
Inst_VOP3::instSize() const
Inst_VOP3A::instSize() const
{
return 8;
} // instSize
void
Inst_VOP3::generateDisassembly()
Inst_VOP3A::generateDisassembly()
{
std::stringstream dis_stream;
dis_stream << _opcode << " ";
@@ -1272,7 +1272,7 @@ namespace VegaISA
}
bool
Inst_VOP3::isScalarRegister(int opIdx)
Inst_VOP3A::isScalarRegister(int opIdx)
{
assert(opIdx >= 0);
assert(opIdx < getNumOperands());
@@ -1346,7 +1346,7 @@ namespace VegaISA
}
bool
Inst_VOP3::isVectorRegister(int opIdx)
Inst_VOP3A::isVectorRegister(int opIdx)
{
assert(opIdx >= 0);
assert(opIdx < getNumOperands());
@@ -1420,7 +1420,7 @@ namespace VegaISA
}
int
Inst_VOP3::getRegisterIndex(int opIdx, int num_scalar_regs)
Inst_VOP3A::getRegisterIndex(int opIdx, int num_scalar_regs)
{
assert(opIdx >= 0);
assert(opIdx < getNumOperands());
@@ -1489,10 +1489,9 @@ namespace VegaISA
}
}
// --- Inst_VOP3_SDST_ENC base class methods ---
// --- Inst_VOP3B base class methods ---
Inst_VOP3_SDST_ENC::Inst_VOP3_SDST_ENC(InFmt_VOP3_SDST_ENC *iFmt,
const std::string &opcode)
Inst_VOP3B::Inst_VOP3B(InFmt_VOP3B *iFmt, const std::string &opcode)
: VEGAGPUStaticInst(opcode)
{
// copy first instruction DWORD
@@ -1500,20 +1499,20 @@ namespace VegaISA
// copy second instruction DWORD
extData = ((InFmt_VOP3_1 *)iFmt)[1];
_srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
} // Inst_VOP3_SDST_ENC
} // Inst_VOP3B
Inst_VOP3_SDST_ENC::~Inst_VOP3_SDST_ENC()
Inst_VOP3B::~Inst_VOP3B()
{
} // ~Inst_VOP3_SDST_ENC
} // ~Inst_VOP3B
int
Inst_VOP3_SDST_ENC::instSize() const
Inst_VOP3B::instSize() const
{
return 8;
} // instSize
void
Inst_VOP3_SDST_ENC::generateDisassembly()
Inst_VOP3B::generateDisassembly()
{
std::stringstream dis_stream;
dis_stream << _opcode << " ";
@@ -1557,7 +1556,7 @@ namespace VegaISA
}
bool
Inst_VOP3_SDST_ENC::isScalarRegister(int opIdx)
Inst_VOP3B::isScalarRegister(int opIdx)
{
assert(opIdx >= 0);
assert(opIdx < getNumOperands());
@@ -1631,7 +1630,7 @@ namespace VegaISA
}
bool
Inst_VOP3_SDST_ENC::isVectorRegister(int opIdx)
Inst_VOP3B::isVectorRegister(int opIdx)
{
assert(opIdx >= 0);
assert(opIdx < getNumOperands());
@@ -1705,7 +1704,7 @@ namespace VegaISA
}
int
Inst_VOP3_SDST_ENC::getRegisterIndex(int opIdx, int num_scalar_regs)
Inst_VOP3B::getRegisterIndex(int opIdx, int num_scalar_regs)
{
assert(opIdx >= 0);
assert(opIdx < getNumOperands());

24
src/arch/amdgpu/vega/insts/op_encodings.hh
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@@ -350,11 +350,11 @@ namespace VegaISA
InFmt_VINTRP instData;
}; // Inst_VINTRP
class Inst_VOP3 : public VEGAGPUStaticInst
class Inst_VOP3A : public VEGAGPUStaticInst
{
public:
Inst_VOP3(InFmt_VOP3*, const std::string &opcode, bool sgpr_dst);
~Inst_VOP3();
Inst_VOP3A(InFmt_VOP3A*, const std::string &opcode, bool sgpr_dst);
~Inst_VOP3A();
int instSize() const override;
void generateDisassembly() override;
@@ -365,12 +365,12 @@ namespace VegaISA
protected:
// first instruction DWORD
InFmt_VOP3 instData;
InFmt_VOP3A instData;
// second instruction DWORD
InFmt_VOP3_1 extData;
private:
bool hasSecondDword(InFmt_VOP3 *);
bool hasSecondDword(InFmt_VOP3A *);
/**
* the v_cmp and readlane instructions in the VOP3
* encoding are unique because they are the only
@@ -382,13 +382,13 @@ namespace VegaISA
* from which we are reading.
*/
const bool sgprDst;
}; // Inst_VOP3
}; // Inst_VOP3A
class Inst_VOP3_SDST_ENC : public VEGAGPUStaticInst
class Inst_VOP3B : public VEGAGPUStaticInst
{
public:
Inst_VOP3_SDST_ENC(InFmt_VOP3_SDST_ENC*, const std::string &opcode);
~Inst_VOP3_SDST_ENC();
Inst_VOP3B(InFmt_VOP3B*, const std::string &opcode);
~Inst_VOP3B();
int instSize() const override;
void generateDisassembly() override;
@@ -399,13 +399,13 @@ namespace VegaISA
protected:
// first instruction DWORD
InFmt_VOP3_SDST_ENC instData;
InFmt_VOP3B instData;
// second instruction DWORD
InFmt_VOP3_1 extData;
private:
bool hasSecondDword(InFmt_VOP3_SDST_ENC *);
}; // Inst_VOP3_SDST_ENC
bool hasSecondDword(InFmt_VOP3B *);
}; // Inst_VOP3B
class Inst_DS : public VEGAGPUStaticInst
{