configs: RubySimpleSystem and simple ruby_fs.py script

This patch is providing a minimal ruby powered script
for Arm simulations

Change-Id: Ifb2d827362e2d5de5d15c70b200598f9f714f7f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43288
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-03-12 20:41:26 +00:00
parent 918a01f42e
commit 47a278c0ad
2 changed files with 287 additions and 0 deletions

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@@ -386,3 +386,26 @@ class SimpleSystem(BaseSimpleSystem):
def attach_pci(self, dev):
self.realview.attachPciDevice(dev, self.iobus)
class ArmRubySystem(BaseSimpleSystem):
"""
Meant to be used with ruby
"""
def __init__(self, mem_size, platform=None, **kwargs):
super(ArmRubySystem, self).__init__(mem_size, platform, **kwargs)
self._dma_ports = []
self._mem_ports = []
def connect(self):
self.realview.attachOnChipIO(self.iobus,
dma_ports=self._dma_ports, mem_ports=self._mem_ports)
self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
for cluster in self._clusters:
for i, cpu in enumerate(cluster.cpus):
self.ruby._cpu_ports[i].connectCpuPorts(cpu)
def attach_pci(self, dev):
self.realview.attachPciDevice(dev, self.iobus,
dma_ports=self._dma_ports)

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@@ -0,0 +1,264 @@
# Copyright (c) 2016-2017, 2020-2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import m5
from m5.util import addToPath
from m5.objects import *
from m5.options import *
import optparse
m5.util.addToPath('../..')
from common import MemConfig
from common import ObjectList
from common import Options
from common import SysPaths
from common.cores.arm import HPI
from ruby import Ruby
import devices
default_kernel = 'vmlinux.arm64'
default_disk = 'linaro-minimal-aarch64.img'
default_root_device = '/dev/vda1'
# Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
# the cache class may be 'None' if the particular cache is not present.
cpu_types = {
"noncaching" : ( NonCachingSimpleCPU, None, None, None, None),
"minor" : (MinorCPU,
devices.L1I, devices.L1D,
devices.WalkCache,
devices.L2),
"hpi" : ( HPI.HPI,
HPI.HPI_ICache, HPI.HPI_DCache,
HPI.HPI_WalkCache,
HPI.HPI_L2)
}
def create_cow_image(name):
"""Helper function to create a Copy-on-Write disk image"""
image = CowDiskImage()
image.child.image_file = SysPaths.disk(name)
return image
def config_ruby(system, options):
cpus = []
for cluster in system.cpu_cluster:
for cpu in cluster.cpus:
cpus.append(cpu)
Ruby.create_system(options, True, system, system.iobus,
system._dma_ports, system.realview.bootmem,
cpus)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(
clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
def create(args):
''' Create and configure the system object. '''
if args.script and not os.path.isfile(args.script):
print("Error: Bootscript %s does not exist" % args.script)
sys.exit(1)
cpu_class = cpu_types[args.cpu][0]
mem_mode = cpu_class.memory_mode()
system = devices.ArmRubySystem(args.mem_size,
mem_mode=mem_mode,
workload=ArmFsLinux(
object_file=
SysPaths.binary(args.kernel)),
readfile=args.script)
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(system,
args.num_cpus,
args.cpu_freq, "1.0V",
*cpu_types[args.cpu]),
]
# Add the PCI devices we need for this system. The base system
# doesn't have any PCI devices by default since they are assumed
# to be added by the configuration scripts needing them.
system.pci_devices = [
# Create a VirtIO block device for the system's boot
# disk. Attach the disk image using gem5's Copy-on-Write
# functionality to avoid writing changes to the stored copy of
# the disk image.
PciVirtIO(vio=VirtIOBlock(image=create_cow_image(args.disk_image))),
]
# Attach the PCI devices to the system. The helper method in the
# system assigns a unique PCI bus ID to each of the devices and
# connects them to the IO bus.
for dev in system.pci_devices:
system.attach_pci(dev)
config_ruby(system, args)
# Wire up the system's memory system
system.connect()
# Setup gem5's minimal Linux boot loader.
system.realview.setupBootLoader(system, SysPaths.binary)
if args.dtb:
system.workload.dtb_filename = args.dtb
else:
# No DTB specified: autogenerate DTB
system.workload.dtb_filename = \
os.path.join(m5.options.outdir, 'system.dtb')
system.generateDtb(system.workload.dtb_filename)
# Linux boot command flags
kernel_cmd = [
# Tell Linux to use the simulated serial port as a console
"console=ttyAMA0",
# Hard-code timi
"lpj=19988480",
# Disable address space randomisation to get a consistent
# memory layout.
"norandmaps",
# Tell Linux where to find the root disk image.
"root=%s" % args.root_device,
# Mount the root disk read-write by default.
"rw",
# Tell Linux about the amount of physical memory present.
"mem=%s" % args.mem_size,
]
system.workload.command_line = " ".join(kernel_cmd)
return system
def run(args):
cptdir = m5.options.outdir
if args.checkpoint:
print("Checkpoint directory: %s" % cptdir)
while True:
event = m5.simulate()
exit_msg = event.getCause()
if exit_msg == "checkpoint":
print("Dropping checkpoint at tick %d" % m5.curTick())
cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick())
m5.checkpoint(os.path.join(cpt_dir))
print("Checkpoint done.")
else:
print(exit_msg, " @ ", m5.curTick())
break
sys.exit(event.getCode())
def main():
parser = optparse.OptionParser()
parser.add_option("--dtb", type=str, default=None,
help="DTB file to load")
parser.add_option("--kernel", type=str, default=default_kernel,
help="Linux kernel")
parser.add_option("--disk-image", type=str,
default=default_disk,
help="Disk to instantiate")
parser.add_option("--root-device", type=str,
default=default_root_device,
help="OS device name for root partition (default: {})"
.format(default_root_device))
parser.add_option("--script", type=str, default="",
help = "Linux bootscript")
parser.add_option("--cpu", type="choice", choices=list(cpu_types.keys()),
default="minor",
help="CPU model to use")
parser.add_option("--cpu-freq", type=str, default="4GHz")
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--checkpoint", action="store_true")
parser.add_option("--restore", type=str, default=None)
parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_option("--mem-channels", type="int", default=1,
help = "number of memory channels")
parser.add_option("--mem-ranks", type="int", default=None,
help = "number of memory ranks per channel")
parser.add_option("--mem-size", action="store", type="string",
default="2GiB",
help="Specify the physical memory size (single memory)")
parser.add_option("--enable-dram-powerdown", action="store_true",
help="Enable low-power states in DRAMInterface")
parser.add_option("--mem-channels-intlv", type="int", default=0,
help="Memory channels interleave")
parser.add_option("--num-dirs", type="int", default=1)
parser.add_option("--num-l2caches", type="int", default=1)
parser.add_option("--num-l3caches", type="int", default=1)
parser.add_option("--l1d_size", type="string", default="64kB")
parser.add_option("--l1i_size", type="string", default="32kB")
parser.add_option("--l2_size", type="string", default="2MB")
parser.add_option("--l3_size", type="string", default="16MB")
parser.add_option("--l1d_assoc", type="int", default=2)
parser.add_option("--l1i_assoc", type="int", default=2)
parser.add_option("--l2_assoc", type="int", default=8)
parser.add_option("--l3_assoc", type="int", default=16)
parser.add_option("--cacheline_size", type="int", default=64)
Ruby.define_options(parser)
(options, args) = parser.parse_args()
root = Root(full_system=True)
root.system = create(options)
if options.restore is not None:
m5.instantiate(options.restore)
else:
m5.instantiate()
run(options)
if __name__ == "__m5_main__":
main()