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arch-vega: Add Vega-specific opcodes

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The opcodes aren't implemented yet, returning nullptr

Change-Id: I700c2158035aea84e6365a32d53304accab59d96
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42208
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Kyle Roarty
2019-06-28 15:19:56 -04:00
committed by Matt Sinclair
parent f85a861594
commit 9ddfe09649
2 changed files with 1668 additions and 236 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1722
src/arch/amdgpu/vega/decoder.cc
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File diff suppressed because it is too large Load Diff

182
src/arch/amdgpu/vega/gpu_decoder.hh
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@@ -66,13 +66,14 @@ namespace VegaISA
static IsaDecodeMethod tableSubDecode_OP_MTBUF[16];
static IsaDecodeMethod tableSubDecode_OP_MUBUF[128];
static IsaDecodeMethod tableSubDecode_OP_SCRATCH[128];
static IsaDecodeMethod tableSubDecode_OP_SMEM[64];
static IsaDecodeMethod tableSubDecode_OP_SMEM[256];
static IsaDecodeMethod tableSubDecode_OP_SOP1[256];
static IsaDecodeMethod tableSubDecode_OP_SOPC[128];
static IsaDecodeMethod tableSubDecode_OP_SOPP[128];
static IsaDecodeMethod tableSubDecode_OP_VINTRP[4];
static IsaDecodeMethod tableSubDecode_OP_VOP1[256];
static IsaDecodeMethod tableSubDecode_OP_VOPC[256];
static IsaDecodeMethod tableSubDecode_OP_VOP3P[128];
GPUStaticInst* decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst);
@@ -435,18 +436,42 @@ namespace VegaISA
GPUStaticInst* decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_U64_U32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_I64_I32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_LEGACY_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_LEGACY_U16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_LEGACY_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_PERM_B32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_FMA_LEGACY_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_U32_U16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_I32_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_XAD_U32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MIN3_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MIN3_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MIN3_U16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAX3_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAX3_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAX3_U16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MED3_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MED3_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MED3_U16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_LSHL_ADD_U32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_ADD_LSHL_U32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_ADD3_U32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_LSHL_OR_B32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_AND_OR_B32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_OR3_B32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_U16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MAD_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_PERM_B32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_FMA_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_INTERP_P1_F32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_INTERP_P2_F32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_INTERP_P2_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_ADD_F64(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_MUL_F64(MachInst);
@@ -472,6 +497,13 @@ namespace VegaISA
GPUStaticInst* decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_PKNORM_I16_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_PKNORM_U16_F16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_ADD_I32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_SUB_I32(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_ADD_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_SUB_I16(MachInst);
GPUStaticInst* decode_OPU_VOP3__V_PACK_B32_F16(MachInst);
GPUStaticInst* decode_OP_DS__DS_ADD_U32(MachInst);
GPUStaticInst* decode_OP_DS__DS_SUB_U32(MachInst);
GPUStaticInst* decode_OP_DS__DS_RSUB_U32(MachInst);
@@ -494,6 +526,7 @@ namespace VegaISA
GPUStaticInst* decode_OP_DS__DS_MAX_F32(MachInst);
GPUStaticInst* decode_OP_DS__DS_NOP(MachInst);
GPUStaticInst* decode_OP_DS__DS_ADD_F32(MachInst);
GPUStaticInst* decode_OP_DS__DS_WRITE_ADDTID_B32(MachInst);
GPUStaticInst* decode_OP_DS__DS_WRITE_B8(MachInst);
GPUStaticInst* decode_OP_DS__DS_WRITE_B16(MachInst);
GPUStaticInst* decode_OP_DS__DS_ADD_RTN_U32(MachInst);
@@ -548,6 +581,14 @@ namespace VegaISA
GPUStaticInst* decode_OP_DS__DS_CMPST_F64(MachInst);
GPUStaticInst* decode_OP_DS__DS_MIN_F64(MachInst);
GPUStaticInst* decode_OP_DS__DS_MAX_F64(MachInst);
GPUStaticInst* decode_OP_DS__DS_WRITE_B8_D16_HI(MachInst);
GPUStaticInst* decode_OP_DS__DS_WRITE_B16_D16_HI(MachInst);
GPUStaticInst* decode_OP_DS__DS_READ_U8_D16(MachInst);
GPUStaticInst* decode_OP_DS__DS_READ_U8_D16_HI(MachInst);
GPUStaticInst* decode_OP_DS__DS_READ_I8_D16(MachInst);
GPUStaticInst* decode_OP_DS__DS_READ_I8_D16_HI(MachInst);
GPUStaticInst* decode_OP_DS__DS_READ_U16_D16(MachInst);
GPUStaticInst* decode_OP_DS__DS_READ_U16_D16_HI(MachInst);
GPUStaticInst* decode_OP_DS__DS_ADD_RTN_U64(MachInst);
GPUStaticInst* decode_OP_DS__DS_SUB_RTN_U64(MachInst);
GPUStaticInst* decode_OP_DS__DS_RSUB_RTN_U64(MachInst);
@@ -594,6 +635,7 @@ namespace VegaISA
GPUStaticInst* decode_OP_DS__DS_GWS_SEMA_BR(MachInst);
GPUStaticInst* decode_OP_DS__DS_GWS_SEMA_P(MachInst);
GPUStaticInst* decode_OP_DS__DS_GWS_BARRIER(MachInst);
GPUStaticInst* decode_OP_DS__DS_READ_ADDTID_B32(MachInst);
GPUStaticInst* decode_OP_DS__DS_CONSUME(MachInst);
GPUStaticInst* decode_OP_DS__DS_APPEND(MachInst);
GPUStaticInst* decode_OP_DS__DS_ORDERED_COUNT(MachInst);
@@ -771,12 +813,15 @@ namespace VegaISA
GPUStaticInst* decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4H(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_L(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_B(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4H_PCK(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER8H_PCK(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst);
GPUStaticInst* decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst);
@@ -844,11 +889,21 @@ namespace VegaISA
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_WBINVL1(MachInst);
GPUStaticInst* decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst);
@@ -905,6 +960,9 @@ namespace VegaISA
GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORDX4(MachInst);
GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORDX8(MachInst);
GPUStaticInst* decode_OP_SMEM__S_LOAD_DWORDX16(MachInst);
GPUStaticInst* decode_OP_SMEM__S_SCRATCH_LOAD_DWORD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst);
@@ -913,6 +971,9 @@ namespace VegaISA
GPUStaticInst* decode_OP_SMEM__S_STORE_DWORD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_STORE_DWORDX2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_STORE_DWORDX4(MachInst);
GPUStaticInst* decode_OP_SMEM__S_SCRATCH_STORE_DWORD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst);
@@ -924,6 +985,60 @@ namespace VegaISA
GPUStaticInst* decode_OP_SMEM__S_MEMREALTIME(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATC_PROBE(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst);
GPUStaticInst* decode_OP_SMEM__S_DCACHE_DISCARD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_DCACHE_DISCARD_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_ADD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SUB(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_AND(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_OR(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_XOR(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_INC(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_DEC(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SWAP(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_CMPSWAP(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_ADD(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SUB(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SMIN(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_UMIN(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SMAX(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_UMAX(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_AND(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_OR(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_XOR(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_INC(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_DEC(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SWAP_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_ADD_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SUB_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SMIN_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_UMIN_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_SMAX_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_UMAX_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_AND_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_OR_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_XOR_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_INC_X2(MachInst);
GPUStaticInst* decode_OP_SMEM__S_ATOMIC_DEC_X2(MachInst);
GPUStaticInst* decode_OP_SOP1__S_MOV_B32(MachInst);
GPUStaticInst* decode_OP_SOP1__S_MOV_B64(MachInst);
GPUStaticInst* decode_OP_SOP1__S_CMOV_B32(MachInst);
@@ -972,8 +1087,12 @@ namespace VegaISA
GPUStaticInst* decode_OP_SOP1__S_MOVRELD_B64(MachInst);
GPUStaticInst* decode_OP_SOP1__S_CBRANCH_JOIN(MachInst);
GPUStaticInst* decode_OP_SOP1__S_ABS_I32(MachInst);
GPUStaticInst* decode_OP_SOP1__S_MOV_FED_B32(MachInst);
GPUStaticInst* decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst);
GPUStaticInst* decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64(MachInst);
GPUStaticInst* decode_OP_SOP1__S_ORN1_SAVEEXEC_B64(MachInst);
GPUStaticInst* decode_OP_SOP1__S_ANDN1_WREXEC_B64(MachInst);
GPUStaticInst* decode_OP_SOP1__S_ANDN2_WREXEC_B64(MachInst);
GPUStaticInst* decode_OP_SOP1__S_BITREPLICATE_B64_B32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_ADD_U32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_SUB_U32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_ADD_I32(MachInst);
@@ -1018,6 +1137,15 @@ namespace VegaISA
GPUStaticInst* decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst);
GPUStaticInst* decode_OP_SOP2__S_ABSDIFF_I32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst);
GPUStaticInst* decode_OP_SOP2__S_MUL_HI_U32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_MUL_HI_I32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_LSHL1_ADD_U32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_LSHL2_ADD_U32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_LSHL3_ADD_U32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_LSHL4_ADD_U32(MachInst);
GPUStaticInst* decode_OP_SOP2__S_PACK_LL_B32_B16(MachInst);
GPUStaticInst* decode_OP_SOP2__S_PACK_LH_B32_B16(MachInst);
GPUStaticInst* decode_OP_SOP2__S_HH_B32_B16(MachInst);
GPUStaticInst* decode_OP_SOPC__S_CMP_EQ_I32(MachInst);
GPUStaticInst* decode_OP_SOPC__S_CMP_LG_I32(MachInst);
GPUStaticInst* decode_OP_SOPC__S_CMP_GT_I32(MachInst);
@@ -1058,6 +1186,7 @@ namespace VegaISA
GPUStaticInst* decode_OP_SOPK__S_GETREG_B32(MachInst);
GPUStaticInst* decode_OP_SOPK__S_SETREG_B32(MachInst);
GPUStaticInst* decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst);
GPUStaticInst* decode_OP_SOPK__S_CALL_B64(MachInst);
GPUStaticInst* decode_OP_SOPP__S_NOP(MachInst);
GPUStaticInst* decode_OP_SOPP__S_ENDPGM(MachInst);
GPUStaticInst* decode_OP_SOPP__S_BRANCH(MachInst);
@@ -1088,6 +1217,7 @@ namespace VegaISA
GPUStaticInst* decode_OP_SOPP__S_ENDPGM_SAVED(MachInst);
GPUStaticInst* decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst);
GPUStaticInst* decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst);
GPUStaticInst* decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE(MachInst);
GPUStaticInst* decode_OP_VINTRP__V_INTERP_P1_F32(MachInst);
GPUStaticInst* decode_OP_VINTRP__V_INTERP_P2_F32(MachInst);
GPUStaticInst* decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst);
@@ -1100,7 +1230,6 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOP1__V_CVT_F32_U32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_U32_F32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_I32_F32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_MOV_FED_B32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_F16_F32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_F32_F16(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst);
@@ -1145,6 +1274,7 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_FREXP_MANT_F32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CLREXCP(MachInst);
GPUStaticInst* decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_F16_U16(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_F16_I16(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_U16_F16(MachInst);
@@ -1165,6 +1295,10 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOP1__V_COS_F16(MachInst);
GPUStaticInst* decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_NORM_I16_F16(MachInst);
GPUStaticInst* decode_OP_VOP1__V_CVT_NORM_U16_F16(MachInst);
GPUStaticInst* decode_OP_VOP1__V_SAT_PK_U8_I16(MachInst);
GPUStaticInst* decode_OP_VOP1__V_SWAP_B32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_CNDMASK_B32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_ADD_F32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUB_F32(MachInst);
@@ -1190,12 +1324,12 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOP2__V_MAC_F32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_MADMK_F32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_MADAK_F32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_ADD_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUB_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBREV_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_ADDC_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBB_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBBREV_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_ADD_CO_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUB_CO_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBREV_CO_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_ADDC_CO_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBB_CO_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBBREV_CO_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_ADD_F16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUB_F16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBREV_F16(MachInst);
@@ -1217,6 +1351,9 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOP2__V_MIN_U16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_MIN_I16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_LDEXP_F16(MachInst);
GPUStaticInst* decode_OP_VOP2__V_ADD_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUB_U32(MachInst);
GPUStaticInst* decode_OP_VOP2__V_SUBREV_U32(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMP_CLASS_F32(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMP_CLASS_F64(MachInst);
@@ -1415,6 +1552,28 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOPC__V_CMPX_NE_U64(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMPX_GE_U64(MachInst);
GPUStaticInst* decode_OP_VOPC__V_CMPX_T_U64(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MAD_I16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MUL_LO_U16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_ADD_I16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_SUB_I16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_LSHLREV_B16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_LSHRREV_B16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_ASHRREV_I16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MAX_I16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MIN_I16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MAD_U16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_ADD_U16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_SUB_U16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MAX_U16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MIN_U16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_FMA_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_ADD_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MUL_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MIN_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MAX_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_MAD_MIX_F32(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_MAD_MIXLO_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_MAD_MIXHI_F16(MachInst);
GPUStaticInst* subDecode_OPU_VOP3(MachInst);
GPUStaticInst* subDecode_OP_DS(MachInst);
GPUStaticInst* subDecode_OP_FLAT(MachInst);
@@ -1428,6 +1587,7 @@ namespace VegaISA
GPUStaticInst* subDecode_OP_VINTRP(MachInst);
GPUStaticInst* subDecode_OP_VOP1(MachInst);
GPUStaticInst* subDecode_OP_VOPC(MachInst);
GPUStaticInst* subDecode_OP_VOP3P(MachInst);
GPUStaticInst* decode_invalid(MachInst);
};