derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-x86: Move (most) non-public values out of registers.hh.

Browse Source 
The unnecessary DependenceTags is already being removed by another
pending change, and so is left in place for that to remove. Once that's
happened, the regs/*.hh includes can be removed, and there may be other
include related tangles to sort out.

Change-Id: I1c02aa8fd2f2045017609b70523b3519c2a92b03
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41742
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-02-22 03:20:18 -08:00
parent 376e6d99aa
commit 124f82c109
9 changed files with 24 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/x86/insts/static_inst.cc
View File

@@ -240,13 +240,13 @@ X86StaticInst::printMem(std::ostream &os, uint8_t segment,
os << "rip";
someAddr = true;
} else {
if (scale != 0 && index != ZeroReg) {
if (scale != 0 && index != NUM_INTREGS) {
if (scale != 1)
ccprintf(os, "%d*", scale);
printReg(os, InstRegIndex(index), addressSize);
someAddr = true;
}
if (base != ZeroReg) {
if (base != NUM_INTREGS) {
if (someAddr)
os << " + ";
printReg(os, InstRegIndex(base), addressSize);

2
src/arch/x86/isa.cc
View File

@@ -182,7 +182,7 @@ ISA::copyRegsFrom(ThreadContext *src)
for (int i = 0; i < NumFloatRegs; ++i)
tc->setFloatRegFlat(i, src->readFloatRegFlat(i));
//copy condition-code regs
for (int i = 0; i < NumCCRegs; ++i)
for (int i = 0; i < NUM_CCREGS; ++i)
tc->setCCRegFlat(i, src->readCCRegFlat(i));
copyMiscRegs(src, tc);
tc->pcState(src->pcState());

4
src/arch/x86/isa/specialize.isa
View File

@@ -250,12 +250,12 @@ let {{
if opType.tag == "X":
env.addToDisassembly(
'''printMem(out, env.seg,
1, X86ISA::ZeroReg, X86ISA::INTREG_RSI, 0,
1, X86ISA::NUM_INTREGS, X86ISA::INTREG_RSI, 0,
env.addressSize, false);''')
else:
env.addToDisassembly(
'''printMem(out, SEGMENT_REG_ES,
1, X86ISA::ZeroReg, X86ISA::INTREG_RDI, 0,
1, X86ISA::NUM_INTREGS, X86ISA::INTREG_RDI, 0,
env.addressSize, false);''')
Name += "_M"
else:

2
src/arch/x86/linux/linux.hh
View File

@@ -62,7 +62,7 @@ class X86Linux : public Linux
}
if (stack)
ctc->setIntReg(X86ISA::StackPointerReg, stack);
ctc->setIntReg(X86ISA::INTREG_RSP, stack);
}
class SyscallABI {};

2
src/arch/x86/process.cc
View File

@@ -981,7 +981,7 @@ X86Process::argsInit(int pageSize,
ThreadContext *tc = system->threads[contextIds[0]];
// Set the stack pointer register
tc->setIntReg(StackPointerReg, stack_min);
tc->setIntReg(INTREG_RSP, stack_min);
// There doesn't need to be any segment base added in since we're dealing
// with the flat segmentation model.

19
src/arch/x86/registers.hh
View File

@@ -41,23 +41,14 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/ccr.hh"
#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
namespace X86ISA
{
const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
const int NumCCRegs = NUM_CCREGS;
// Each 128 bit xmm register is broken into two effective 64 bit registers.
// Add 8 for the indices that are mapped over the fp stack
const int NumFloatRegs =
NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
// These enumerate all the registers for dependence tracking.
enum DependenceTags
{
@@ -66,14 +57,12 @@ enum DependenceTags
// we just start at (1 << 7) == 128.
FP_Reg_Base = 128,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
Misc_Reg_Base = CC_Reg_Base + NUM_CCREGS,
Max_Reg_Index = Misc_Reg_Base + NUM_MISCREGS
};
// semantically meaningful register indices
//There is no such register in X86
// There is no such register in X86.
const int ZeroReg = NUM_INTREGS;
const int StackPointerReg = INTREG_RSP;
// Not applicable to x86
using VecElem = ::DummyVecElem;

5
src/arch/x86/regs/float.hh
View File

@@ -148,6 +148,11 @@ namespace X86ISA
{
return FLOATREG_FPR((top + index + 8) % 8);
}
// Each 128 bit xmm register is broken into two effective 64 bit registers.
// Add 8 for the indices that are mapped over the fp stack
const int NumFloatRegs =
NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
}
#endif // __ARCH_X86_FLOATREGS_HH__

4
src/arch/x86/regs/int.hh
View File

@@ -169,6 +169,10 @@ namespace X86ISA
index = (index - 4) | foldBit;
return (IntRegIndex)index;
}
const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs =
NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
}
#endif // __ARCH_X86_INTREGS_HH__

6
src/arch/x86/utility.cc
View File

@@ -40,11 +40,13 @@
#include "arch/x86/interrupts.hh"
#include "arch/x86/mmu.hh"
#include "arch/x86/registers.hh"
#include "arch/x86/regs/ccr.hh"
#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/base.hh"
#include "fputils/fp80.h"
#include "sim/full_system.hh"
namespace X86ISA
{