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10760 Commits

Author SHA1 Message Date
Gabe Black
cac49d4e47 arch,cpu,sim: Get rid of the microcode ROM stub code. 
This code, including a switching header file, is no longer necessary
because ROM based microops are now handled by the decoder itself.

Change-Id: Ie3ea4a7371dec22993ede80e2acd1df7cd1ecf59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32899
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-25 12:41:30 +00:00
Gabe Black
a3e113239b cpu,arch: Delegate fetching ROM microops to the decoder. 
In most cases, the microcode ROM doesn't actually do anything. The
structural existence of a microcode ROM doesn't make sense in the
general case, and in architectures that know they have one and need to
interact with it, they can cast their decoder into an arch specific type
and access the ROM that way.

Change-Id: I25b67bfe65df1fdb84eb5bc894cfcb83da1ce64b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32898
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-25 12:41:20 +00:00
Gabe Black
9154f23d2c x86: Use default initializers to simplify the decoder constructor. 
Change-Id: I76f1fe9a58a26f26c204cb0b9bab050a22d289c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-25 12:41:02 +00:00
Gabe Black
119bc80cca x86: Remove unnecessary includes from isa_traits.hh. 
These includes are not used in this header file, and if they're needed
by other source it should include them directly.

Change-Id: I7d17d7c7fcc1020d85f1257059d2c2057b0c461d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33196
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-25 06:45:57 +00:00
Gabe Black
9d8273e341 sim: Style fixes in the base Fault classes. 
Change-Id: Iff8588aba929b3909ca1b5ec0e494acb8f838543
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33280
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
 2020-08-25 06:33:27 +00:00
Gabe Black
5c1213d63d x86: Style fixes in x86's fault implementations. 
Change-Id: I320877a7e753eae5ffba2421e6dfe23b52352664
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33279
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
 2020-08-25 06:25:03 +00:00
Gabe Black
0677b1596a x86: Replace "is not" with "!=" in fpop.isa. 
Some variables were being compared against some constants with "is not",
which is not correct since it will compare for identity rather than
equivalence. There was a long standing build warning from this, but it
wasn't clear where the error was coming from since it was in python
interpreted from a string in the ISA description.

This change replaces "is not" in those two places with "!=".

Change-Id: I0c4d038af6e047ffd79f8171713e8e998e840e3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33283
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
 2020-08-25 06:24:49 +00:00
Gabe Black
634562f5dd misc: Replace some includes of arch/isa_traits.hh. 
In sim/vma.hh, the include was indirectly getting the definition of
DPRINTF. It was replaced with an include of base/trace.hh which actually
provides that definition.

In the indirect branch predictor, it was being used to get the
definition of TheISA::PCState. This should come from arch/types.hh
instead.

Change-Id: I6de08f196499c85b54edde09d654902cc766c2eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33195
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-25 03:22:22 +00:00
Emily Brickey
c5522f2b32 arch-riscv, arch-x86: convert tlb to new style stats 
Change-Id: Ie2754d861a658fde0acdda30cbcb91e02029e33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32835
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-24 22:15:37 +00:00
Emily Brickey
8f0fa8ed78 arch-mips, arch-power: removed unused stats 
Change-Id: Ic44943eaefab027d6dc665e531f827202b353093
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32834
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-24 22:15:37 +00:00
Juan M. Cebrian
9b8cc2f5c3 arch-x86,cpu: Fix bpred by annotating branch instructions in x86 
Original Creator: Adria Armejach.

Branch instructions needed to be annotated in x86 as direct/indirect and conditional/unconditional. These annotations where not present causing the branch predictor to misbehave, not using the BTB. In addition, logic to determine the real branch target at decode needed to be added as it was also missing.

Change-Id: I91e707452c1825b9bb4ae75c3f599da489ae5b9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29154
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-24 16:20:06 +00:00
Gabe Black
9d1278d551 misc: Delete the critical path annotation code. 
This code was at least a little Alpha specific, and now that Alpha is
gone it can no longer be compiled. We could either fix it up to work
with other/all ISAs or delete it, and the consensus was to delete it. It
could potentially be revived in the future by retrieving it from version
control.

Change-Id: Ied073f2b9b166951ecba3442cd762eb19bc690b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32954
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-23 03:17:13 +00:00
Gabe Black
1cf7b28ba6 mem: Use getGuestByteOrder in the indirect memory prefetcher. 
Use that instead of accessing TheISA::GuestByteOrder directly.

Change-Id: I6fbeb7501aceadb95739bb482215097af18da2fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32926
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-21 22:18:23 +00:00
Ian Jiang
03976aa582 arch-riscv: Add float registers in copyRegs 
The origin copyRegs() does not include float registers.
This patch fixes the problem.

Change-Id: If4ad04b1eda6035486197879ff3e04ff32dd87bb
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32934
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-21 00:51:26 +00:00
Gabe Black
f1840c9951 arch: Eliminate the unused HasUnalignedMemAcc constant. 
Change-Id: Iaf9346df57336216c09979fe1d931701c6b7ddf6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32923
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 05:43:50 +00:00
Gabe Black
1981c3110d arch: Eliminate an unused pair of constants from isa_traits.hh. 
The one questionable use of CurThreadInfoImplemented (always false) and
CurThreadInfoReg (always -1) has been eliminated, making these constants
unnecessary.

Change-Id: Ibfe4f7be7ce5aaf9c5e896146e1b05b3ac752305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32922
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 05:43:24 +00:00
Gabe Black
df8a58895b arch: Make ThreadInfo::curThreadInfo virtual, protected. 
Also remove it's Alpha centric implementation. All existing ISAs will
panic since they all define the guarding constant as false. Even if they
defined it as true, this function assumes that there is necessarily a misc
reg which can be read to find the current thread_info struct, and how
the contents of that register should be manipulated.

This code is already fairly fragile since it depends on things in the
Linux kernel having certain names and relationships with each other, but
that's a larger problem I don't want to fix right now.

Change-Id: Ic107793ebcd25ee25c4d3713c84c1d2b5209f1a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32921
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 05:43:14 +00:00
Gabe Black
7f7f2f0488 x86: Replace getDoubleBits with floatToBits64. 
The getDoubleBits function was used exactly once to find the bit
representation of a double floating point value, which is the same thing
the common floatToBits64 function does. Eliminate x86's one off version,
and use the common one instead.

Change-Id: Icb0cec5a55d81a6eacf1bb5a3c2b8f16c414d0d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32927
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 05:02:47 +00:00
Gabe Black
1f7cc16a70 mem: Use the System object's getGuestByteOrder in AbstractMemory. 
Change-Id: Ifcf3d8dcbee73555b23ec0a8c25572921fca13a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32925
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 05:02:07 +00:00
Gabe Black
345b17af20 arch: Remove the "inline" keyword in ThreadInfo. 
Methods which are defined inline are already implicitly inline, making
that keyword redundant. It's also inconsistently used.

Change-Id: If6ec3e94d126ae52d9c2f0d3e8ca27f1ac600650
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32920
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 04:54:13 +00:00
Gabe Black
fff5b8e745 x86: Fix some style issues in the microcode ROM class. 
Change-Id: I64fb5efbc9f63298c103816503f4718308032eb4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32896
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 04:46:17 +00:00
Gabe Black
32020236cf x86: Style fix in the decoder class. 
Change-Id: If06a8771b5db0fb68e88b16dedfe60fc2ce306d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32894
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 04:45:55 +00:00
Gabe Black
c3d20692c3 arch: Get the byte order from sys and not TheISA::. 
This is a small step which localizes the use of TheISA, hopefully making
it easier to eliminate in the future.

Change-Id: I13472ed69e12a3c753e2dea91b9c7ca813bfc0e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 04:45:35 +00:00
Gabe Black
fee00c6863 kern: Stop using TheISA::GuestByteOrder in Linux::dumpDmesg. 
This value is already read from the system object in that same function.
We should use that instead of getting the value ourselves.

Change-Id: I0a442cd4892f50ad0179884bebf3eb52881c022f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32924
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 01:38:45 +00:00
Gabe Black
937c4b4003 arch: Don't add contents to the TheISA namespace in arch/generic. 
Instead, add what you want other ISAs to be able to use to a generic,
fixed namespace, and then let those other ISAs bring those symbols in
with "using" if they want them.

Change-Id: I15bfaf56e76ffdc3bdb603deef4ad471211f4f24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32929
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 01:36:24 +00:00
Gabe Black
8477866a13 dev,arm: Stop using TheISA in ARM specific files. 
These can use ArmISA since there's no ambiguity about what ISA is being
used with those files.

Change-Id: I02e8ea0ab70215679eb939adaa949400e878b1ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32928
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 01:36:08 +00:00
Gabe Black
c0f4489220 arch: Fix a small style issue in Linux::ThreadInfo. 
Change-Id: I7f6f938f9412e535df0cbc0687ec9f2de2dbf8e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32918
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 01:08:54 +00:00
Gabe Black
6add4fbc12 cpu: Don't construct and then copy the decoder in SimpleThread. 
The SimpleThread constructor was constructing a temporary copy of the
decoder, and then copying it into it's local version. This copy is a
waste, and also requires there to be a copy operator for the Decoder.

Change-Id: I1123b4ec767e08ceb2f108b3a6b19ca18d7c677c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32900
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 01:08:25 +00:00
Gabe Black
65c8b246ba arch: Create a base class for decoders. 
This base class doesn't actually hold anything yet, it's just a place to
add shared functionality or interfaces later.

Change-Id: Ia33217bd78b1d1ff3df3b2202095576a4e5d8153
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32897
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-20 01:07:13 +00:00
Gabe Black
34a03ba4cc misc: Replace scalar TypedBufferArg with VPtr. 
Change-Id: Ic8460ad133e3512c103b14820d90ee3df987d78d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31755
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
 2020-08-19 12:04:18 +00:00
Ian Jiang
243e240ee3 arch-riscv: Fix disassembling of CSR instructions 
The correct formats of CSR instructions are:
- mnemonic rd, csr, rs1
- mnemonic rd, csr, uimm

This patch fixes the problem.

Change-Id: Ie34e67a523e3458b90c27ca19f8c660b4775da6f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32814
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-19 05:03:46 +00:00
Kyle Roarty
b872f02ab1 configs,gpu-compute,mem-ruby: connect gmTokenPorts in apu_se 
This patch adds gmTokenPorts to the ComputeUnit and RubyGPUCoalescer
python classes so the gmTokenPorts can be connected in apu_se.

Change-Id: Icf3cb05c757754d6935b46f14e4b1b1d5072c4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32677
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 23:47:16 +00:00
Gabe Black
17afbc2416 misc: Rename CallbackQueue2 to CallbackQueue. 
Now that the original CallbackQueue has been removed, CallbackQueue2 can
fully take it's place.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I925f647cbbd393045a22f7cbd5d8b4d7d23d19b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32651
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 23:21:30 +00:00
Gabe Black
1c6992978f base: Get rid the Callback type. 
This leaves only the lambda/std::function based CallbackQueue2, soon to
be renamed just CallbackQueue.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I4e2fd3b7b684c414be6db0e268284ab63e6cfdff
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32650
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 23:21:18 +00:00
Gabe Black
35f0e8f4f3 dev: Replace Callback in the virtio device with a lambda. 
Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Ia628ceb0080b11b81c7eee82e7c8c0049b2cd62f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32649
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 23:21:04 +00:00
Gabe Black
637aa00218 dev: Replace the Callback class with lambdas in ARM's flash devices. 
Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I2694dd1952b7412c27c83c9d15d4645899bd28e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32648
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 23:20:58 +00:00
Gabe Black
02de96cb80 dev: Use lambdas instead of the Callback type for serial devices. 
Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Idb87fa0b90d14981fd61f997285f61b2ef304227
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32647
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 19:53:59 +00:00
Gabe Black
0f750ff2c2 sim: Delete the unused PowerStateDumpCallback. 
Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I8e66f31a3a6a82564d9525021ada49ce52beb1fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32646
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 19:53:48 +00:00
Gabe Black
9ed3c7668b misc: Make the stats callbacks use CallbackQueue2. 
Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Idcbe04bdf4299925f321aa0ece263d86ed3fc8df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32645
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 19:53:31 +00:00
Emily Brickey
a65eed883b arch-arm: convert tlb to new style stats 
Change-Id: I2a3f138b53496be6361a1a2b81fa471a56a4dc10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32794
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 16:35:02 +00:00
Giacomo Travaglini
eb1ac7a011 arch-arm: Early checking if debug is enabled in TLB 
The patch is aiming at speeding up gem5 execution.  The TLB::translateFs
is in the critical path of the simulator: every fetch + ld/st will make
use of it.
Checking all the time for a breakpoint during fetch is rather expensive;
it is better to make use of the cached booleans in SelfDebug to do an
early check to see if any of
Watchpoint/Breakpopint/VectorCatch/SoftwareStep is enabled.
Most workloads won't use them so there's no point on calling the
testDebug method

Change-Id: I0189b84e0dc2e081acce04ff44787b9f1014477c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32776
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 13:04:58 +00:00
Giacomo Travaglini
81ad7e66db arch-arm: Rename SelfDebug member variables 
* enableFlag -> mde
The "enableFlag" variable, enabling the Breakpoint, Watchpoint, Vector
Catch exceptions is actually the cached version of MDSCR_EL1.MDE. The
"enableFlag" name looks too general as it's not covering the Software
Step exception case.

* bKDE -> kde
* bSDD -> sdd

The b prefix was likely referring to "breakpoint". However these bitfields
are actually used by watchpoints as well.

Change-Id: I48b762b32b2d763f4c4ceb7dcc28968cfb470fc1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32775
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
 2020-08-18 13:04:58 +00:00
Giacomo Travaglini
b438ec2b1c arch-arm: Remove setters from SoftwareStep 
Motivation:
Those helpers are used and meant to be used by the parent
(SelfDebug) class only. There is no point on exposing them to
the outer world. Better to make SelfDebug a friend class and to
allow it to access children's private data.

Change-Id: Ib945b1aa46742b90062ce7a5de563f164127075f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32774
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 13:04:58 +00:00
Gabe Black
40e8cac306 misc: Make registerExitCallback use CallbackQueue2. 
Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I526d4a19ca4e54a6469a4ee26693c1c0400fcc70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32644
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 11:49:06 +00:00
Gabe Black
316f7d42dc mem: Use the new type of CallbackQueue in the MemBackdoor. 
Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: Ide40528f8c613b46204550d6e6840a7b274a366a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32643
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 11:48:59 +00:00
Gabe Black
4f121c11a2 base: Add a new type of CallbackQueue. 
This type is templated on what arguments the callbacks in it accept, and
it inherits directly from std::list instead of containing one and
forwarding selected members.

This version is called CallbackQueue2, but once all CallbackQueue
instances have been replaced it will be renamed to CallbackQueue.

Issue-on: https://gem5.atlassian.net/browse/GEM5-698
Change-Id: I32ab7454ea8c6a2af31cbcf5d4932a069ace1cb5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32642
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 11:48:51 +00:00
Ian Jiang
96f482fd6c arch-riscv: Fix disassembling of all register instructions 
How many Rs to output in disassembling register instructions? It does
not depend on wheather the register index is zero, but on the count
of source registers.

This patch fixes the problem.

Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-18 01:11:15 +00:00
Emily Brickey
bfc3967695 arch-arm: convert table_walker to new style stats 
Change-Id: I347a72d33e3d0eb9f60ac01dfa2cc82bdbae3cbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32494
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2020-08-17 16:57:00 +00:00
Isaac Sánchez Barrera
7740fd7714 mem-cache,python: Allow custom TLB and events in each prefetcher. 
The `BasePrefetcher` python class had members `_events` and `_tlbs`
defined as lists, meaning that any call to `list.append` on them would
affect `_events` and `_tlbs` for all prefetchers, not just the calling
object.  This change redefines them as instance members to fix the
problem.

Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32394
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
 2020-08-17 11:35:48 +00:00
Giacomo Travaglini
4fbe6cf419 arch-arm: Use isSecure variable for Stage2Lookup 
TLB entries are tagged with the security state of the cpu instead
of the security attribute of the physical address

Change-Id: I728ba1c841de1ec6c1ee03aee012b185c968d078
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32639
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-14 13:07:41 +00:00