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arch-riscv: Fix disassembling of all register instructions

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How many Rs to output in disassembling register instructions? It does
not depend on wheather the register index is zero, but on the count
of source registers.

This patch fixes the problem.

Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ian Jiang
2020-08-14 10:13:41 +08:00
parent bfc3967695
commit 96f482fd6c
1 changed files with 2 additions and 2 deletions
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4
src/arch/riscv/insts/standard.cc
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@@ -48,9 +48,9 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
registerName(_srcRegIdx[0]);
if (_srcRegIdx[1].index() != 0)
if (_numSrcRegs >= 2)
ss << ", " << registerName(_srcRegIdx[1]);
if (_srcRegIdx[2].index() != 0)
if (_numSrcRegs >= 3)
ss << ", " << registerName(_srcRegIdx[2]);
return ss.str();
}