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misc: Delete the critical path annotation code.

Browse Source 
This code was at least a little Alpha specific, and now that Alpha is
gone it can no longer be compiled. We could either fix it up to work
with other/all ISAs or delete it, and the consensus was to delete it. It
could potentially be revived in the future by retrieving it from version
control.

Change-Id: Ied073f2b9b166951ecba3442cd762eb19bc690b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32954
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-08-19 20:14:49 -07:00
parent 1cf7b28ba6
commit 9d1278d551
13 changed files with 5 additions and 2155 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
SConstruct
View File

@@ -1000,8 +1000,6 @@ sticky_vars.AddVariables(
BoolVariable('USE_POSIX_CLOCK', 'Use POSIX Clocks', have_posix_clock),
BoolVariable('USE_FENV', 'Use <fenv.h> IEEE mode control', have_fenv),
BoolVariable('USE_PNG', 'Enable support for PNG images', have_png),
BoolVariable('CP_ANNOTATE', 'Enable critical path annotation capability',
False),
BoolVariable('USE_KVM', 'Enable hardware virtualized (KVM) CPU models',
have_kvm),
BoolVariable('USE_TUNTAP',
@@ -1018,7 +1016,7 @@ sticky_vars.AddVariables(
)
# These variables get exported to #defines in config/*.hh (see src/SConscript).
export_vars += ['USE_FENV', 'TARGET_ISA', 'TARGET_GPU_ISA', 'CP_ANNOTATE',
export_vars += ['USE_FENV', 'TARGET_ISA', 'TARGET_GPU_ISA',
'USE_POSIX_CLOCK', 'USE_KVM', 'USE_TUNTAP', 'PROTOCOL',
'HAVE_PROTOBUF', 'HAVE_VALGRIND',
'HAVE_PERF_ATTR_EXCLUDE_HOST', 'USE_PNG',

1
src/arch/arm/isa/includes.isa
View File

@@ -111,7 +111,6 @@ output exec {{
#endif
#include "base/cp_annotate.hh"
#include "debug/Arm.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"

9
src/base/CPA.py
View File

@@ -1,9 +0,0 @@
from m5.SimObject import SimObject
from m5.params import *
class CPA(SimObject):
type = 'CPA'
cxx_header = "base/cp_annotate.hh"
enabled = Param.Bool(False, "Is Annotation enabled?")
user_apps = VectorParam.String([], "List of apps to get symbols for")

3
src/base/SConscript
View File

@@ -28,9 +28,6 @@
Import('*')
if env['CP_ANNOTATE']:
SimObject('CPA.py')
Source('cp_annotate.cc')
SimObject('Graphics.py')
Source('atomicio.cc')
GTest('atomicio.test', 'atomicio.test.cc', 'atomicio.cc')

1359
src/base/cp_annotate.cc
View File

File diff suppressed because it is too large Load Diff

559
src/base/cp_annotate.hh
View File

@@ -1,559 +0,0 @@
/*
* Copyright (c) 2014 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2006-2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BASE__CP_ANNOTATE_HH__
#define __BASE__CP_ANNOTATE_HH__
#include <list>
#include <map>
#include <memory>
#include <string>
#include <unordered_map>
#include <vector>
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/AnnotateQ.hh"
#include "config/cp_annotate.hh"
#include "config/the_isa.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
#if CP_ANNOTATE
#include "params/CPA.hh"
#endif
class System;
class ThreadContext;
#if !CP_ANNOTATE
class CPA
{
public:
enum flags {
FL_NONE = 0x00,
FL_HW = 0x01,
FL_BAD = 0x02,
FL_QOPP = 0x04,
FL_WAIT = 0x08,
FL_LINK = 0x10,
FL_RESET = 0x20
};
static CPA *cpa() { return NULL; }
static bool available() { return false; }
bool enabled() { return false; }
void swSmBegin(ThreadContext *tc, Addr sm_string,
int32_t sm_id, int32_t flags) { return; }
void swSmEnd(ThreadContext *tc, Addr sm_string) { return; }
void swExplictBegin(ThreadContext *tc, int32_t flags,
Addr st_string) { return; }
void swAutoBegin(ThreadContext *tc, Addr next_pc) { return; }
void swEnd(ThreadContext *tc) { return; }
void swQ(ThreadContext *tc, Addr id, Addr q_string,
int32_t count) { return; }
void swDq(ThreadContext *tc, Addr id, Addr q_string,
int32_t count) { return; }
void swPq(ThreadContext *tc, Addr id, Addr q_string,
int32_t count) { return; }
void swRq(ThreadContext *tc, Addr id, Addr q_string,
int32_t count) { return; }
void swWf(ThreadContext *tc, Addr id, Addr q_string,
Addr sm_string, int32_t count) { return; }
void swWe(ThreadContext *tc, Addr id, Addr q_string,
Addr sm_string, int32_t count) { return; }
void swSq(ThreadContext *tc, Addr id, Addr q_string,
int32_t size, int32_t flags) { return; }
void swAq(ThreadContext *tc, Addr id, Addr q_string,
int32_t size) { return; }
void swLink(ThreadContext *tc, Addr lsm_string,
Addr lsm_id, Addr sm_string) { return; }
void swIdentify(ThreadContext *tc, Addr smi_string) { return; }
uint64_t swGetId(ThreadContext *tc) { return 0; }
void swSyscallLink(ThreadContext *tc, Addr lsm_string,
Addr sm_string) { return; }
void hwBegin(flags f, System *sys, uint64_t frame, std::string sm,
std::string st) { return; }
void hwQ(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL,
int32_t count = 1) { return; }
void hwDq(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL,
int32_t count = 1) { return; }
void hwPq(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL,
int32_t count = 1) { return; }
void hwRq(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL,
int32_t count = 1) { return; }
void hwWf(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL,
int32_t count = 1) { return; }
void hwWe(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL,
int32_t count = 1) { return; }
};
#else
/**
* Provide a hash function for the CPI Id type
*/
namespace std {
template <>
struct hash<std::pair<std::string, uint64_t> >
{
size_t
operator()(const std::pair<std::string, uint64_t>& x) const
{
return hash<std::string>()(x.first);
}
};
}
class CPA : SimObject
{
public:
typedef CPAParams Params;
/** The known operations that are written to the annotation output file. */
enum ops {
OP_BEGIN = 0x01,
OP_WAIT_EMPTY = 0x02,
OP_WAIT_FULL = 0x03,
OP_QUEUE = 0x04,
OP_DEQUEUE = 0x05,
OP_SIZE_QUEUE = 0x08,
OP_PEEK = 0x09,
OP_LINK = 0x0A,
OP_IDENT = 0x0B,
OP_RESERVE = 0x0C
};
/** Flags for the various options.*/
enum flags {
/* no flags */
FL_NONE = 0x00,
/* operation was done on hardware */
FL_HW = 0x01,
/* operation should cause a warning when encountered */
FL_BAD = 0x02,
/* Queue like a stack, not a queue */
FL_QOPP = 0x04,
/* Mark HW state as waiting for some non-resource constraint
* (e.g. wait because SM only starts after 10 items are queued) */
FL_WAIT = 0x08,
/* operation is linking to another state machine */
FL_LINK = 0x10,
/* queue should be completely cleared/reset before executing this
* operation */
FL_RESET = 0x20
};
protected:
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/* struct that is written to the annotation output file */
struct AnnotateData : public Serializable {
Tick time;
uint32_t data;
uint32_t orig_data;
uint16_t sm;
uint16_t stq;
uint8_t op;
uint8_t flag;
uint8_t cpu;
bool dump;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
typedef std::shared_ptr<AnnotateData> AnnDataPtr;
/* header for the annotation file */
struct AnnotateHeader {
uint64_t version;
uint64_t num_recs;
uint64_t key_off;
uint64_t idx_off;
uint32_t key_len;
uint32_t idx_len;
};
AnnotateHeader ah;
std::vector<uint64_t> annotateIdx;
// number of state machines encountered in the simulation
int numSm;
// number of states encountered in the simulation
int numSmt;
// number of states/queues for a given state machine/system respectively
std::vector<int> numSt, numQ;
// number of systems in the simulation
int numSys;
// number of queues in the state machine
int numQs;
// maximum connection id assigned so far
uint64_t conId;
// Convert state strings into state ids
typedef std::unordered_map<std::string, int> SCache;
typedef std::vector<SCache> StCache;
// Convert sm and queue name,id into queue id
typedef std::pair<std::string, uint64_t> Id;
typedef std::unordered_map<Id, int> IdHCache;
typedef std::vector<IdHCache> IdCache;
// Hold mapping of sm and queues to output python
typedef std::vector<std::pair<int, Id> > IdMap;
// System pointer to name,id
typedef std::map<System*, std::pair<std::string, int> > NameCache;
// array of systems each of which is a stack of running sm
typedef std::pair<int, uint64_t> StackId;
typedef std::map<StackId, std::vector<int> > SmStack;
// map of each context and if it's currently in explict state mode
// states are not automatically updated until it leaves
typedef std::map<StackId, bool> SwExpl;
typedef std::map<int,int> IMap;
// List of annotate records have not been written/completed yet
typedef std::list<AnnDataPtr> AnnotateList;
// Maintain link state information
typedef std::map<int, int> LinkMap;
// SC Links
typedef std::unordered_map<Id, AnnDataPtr> ScHCache;
typedef std::vector<ScHCache> ScCache;
AnnotateList data;
// vector indexed by queueid to find current number of elements and bytes
std::vector<int> qSize;
std::vector<int32_t> qBytes;
// Turn state machine string into state machine id (small int)
// Used for outputting key to convert id back into string
SCache smtCache;
// Turn state machine id, state name into state id (small int)
StCache stCache;
// turn system, queue, and queue identify into qid (small int)
// turn system, state, and context into state machine id (small int)
IdCache qCache, smCache;
//Link state machines accross system calls
ScCache scLinks;
// System pointer to name,id
NameCache nameCache;
// Stack of state machines currently nested (should unwind correctly)
SmStack smStack;
// Map of currently outstanding links
LinkMap lnMap;
// If the state machine is currently exculding automatic changes
SwExpl swExpl;
// Last state that a given state machine was in
IMap lastState;
// Hold mapping of sm and queues to output python
IdMap smMap, qMap;
// Items still in queue, used for sanity checking
std::vector<AnnotateList> qData;
void doDq(System *sys, int flags, int cpu, int sm, std::string q, int qi,
int count);
void doQ(System *sys, int flags, int cpu, int sm, std::string q, int qi,
int count);
void doSwSmEnd(System *sys, int cpuid, std::string sm, uint64_t frame);
// Turn a system id, state machine string, state machine id into a small int
// for annotation output
int
getSm(int sysi, std::string si, uint64_t id)
{
int smi;
Id smid = Id(si, id);
smi = smCache[sysi-1][smid];
if (smi == 0) {
smCache[sysi-1][smid] = smi = ++numSm;
assert(smi < 65535);
smMap.push_back(std::make_pair(sysi, smid));
}
return smi;
}
// Turn a state machine string, state string into a small int
// for annotation output
int
getSt(std::string sm, std::string s)
{
int sti, smi;
smi = smtCache[sm];
if (smi == 0)
smi = smtCache[sm] = ++numSmt;
while (stCache.size() < smi) {
//stCache.resize(sm);
stCache.push_back(SCache());
numSt.push_back(0);
}
//assert(stCache.size() == sm);
//assert(numSt.size() == sm);
sti = stCache[smi-1][s];
if (sti == 0)
stCache[smi-1][s] = sti = ++numSt[smi-1];
return sti;
}
// Turn state machine pointer into a smal int for annotation output
int
getSys(System *s)
{
NameCache::iterator i = nameCache.find(s);
if (i == nameCache.end()) {
nameCache[s] = std::make_pair(s->name(), ++numSys);
i = nameCache.find(s);
// might need to put smstackid into map here, but perhaps not
//smStack.push_back(std::vector<int>());
//swExpl.push_back(false);
numQ.push_back(0);
qCache.push_back(IdHCache());
smCache.push_back(IdHCache());
scLinks.push_back(ScHCache());
}
return i->second.second;
}
// Turn queue name, and queue context into small int for
// annotation output
int
getQ(int sys, std::string q, uint64_t id)
{
int qi;
Id qid = Id(q, id);
qi = qCache[sys-1][qid];
if (qi == 0) {
qi = qCache[sys-1][qid] = ++numQs;
assert(qi < 65535);
qSize.push_back(0);
qBytes.push_back(0);
qData.push_back(AnnotateList());
numQ[sys-1]++;
qMap.push_back(std::make_pair(sys, qid));
}
return qi;
}
void swBegin(System *sys, int cpuid, std::string st, uint64_t frame,
bool expl = false, int flags = FL_NONE);
AnnDataPtr add(int t, int f, int c, int sm, int stq, int32_t data=0);
std::ostream *osbin;
bool _enabled;
/** Only allow one CPA object in a system. It doesn't make sense to have
* more that one per simulation because if a part of the system was
* important it would have annotations and queues, and with more than one
* object none of the sanity checking for queues will work. */
static bool exists;
static CPA *_cpa;
std::map<std::string, Loader::SymbolTable*> userApp;
public:
static CPA *cpa() { return _cpa; }
void swSmBegin(ThreadContext *tc);
void swSmEnd(ThreadContext *tc);
void swExplictBegin(ThreadContext *tc);
void swAutoBegin(ThreadContext *tc, Addr next_pc);
void swEnd(ThreadContext *tc);
void swQ(ThreadContext *tc);
void swDq(ThreadContext *tc);
void swPq(ThreadContext *tc);
void swRq(ThreadContext *tc);
void swWf(ThreadContext *tc);
void swWe(ThreadContext *tc);
void swSq(ThreadContext *tc);
void swAq(ThreadContext *tc);
void swLink(ThreadContext *tc);
void swIdentify(ThreadContext *tc);
uint64_t swGetId(ThreadContext *tc);
void swSyscallLink(ThreadContext *tc);
inline void hwBegin(flags f, System *sys, uint64_t frame, std::string sm,
std::string st)
{
if (!enabled())
return;
int sysi = getSys(sys);
int smi = getSm(sysi, sm, frame);
add(OP_BEGIN, FL_HW | f, 0, smi, getSt(sm, st));
if (f & FL_BAD)
warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
}
inline void hwQ(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1)
{
if (!enabled())
return;
int sysi = getSys(sys);
int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid);
DPRINTFS(AnnotateQ, sys,
"hwQ: %s[%#x] cur size %d %d bytes: %d adding: %d\n",
q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count);
doQ(sys, FL_HW | f, 0, getSm(sysi, sm, frame), q, qi, count);
}
inline void hwDq(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1)
{
if (!enabled())
return;
int sysi = getSys(sys);
int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid);
DPRINTFS(AnnotateQ, sys,
"hwDQ: %s[%#x] cur size %d %d bytes: %d removing: %d\n",
q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count);
doDq(sys, FL_HW | f, 0, getSm(sysi,sm, frame), q, qi, count);
}
inline void hwPq(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1)
{
if (!enabled())
return;
int sysi = getSys(sys);
int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid);
DPRINTFS(AnnotateQ, sys,
"hwPQ: %s[%#x] cur size %d %d bytes: %d peeking: %d\n",
q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count);
add(OP_PEEK, FL_HW | f, 0, getSm(sysi, sm, frame), qi, count);
}
inline void hwRq(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1)
{
if (!enabled())
return;
int sysi = getSys(sys);
int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid);
DPRINTFS(AnnotateQ, sys,
"hwRQ: %s[%#x] cur size %d %d bytes: %d reserving: %d\n",
q, qid, qSize[qi-1], qData[qi-1].size(), qBytes[qi-1], count);
add(OP_RESERVE, FL_HW | f, 0, getSm(sysi, sm, frame), qi, count);
}
inline void hwWf(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1)
{
if (!enabled())
return;
int sysi = getSys(sys);
int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid);
add(OP_WAIT_FULL, FL_HW | f, 0, getSm(sysi, sm, frame), qi, count);
}
inline void hwWe(flags f, System *sys, uint64_t frame, std::string sm,
std::string q, uint64_t qid, System *q_sys = NULL, int32_t count = 1)
{
if (!enabled())
return;
int sysi = getSys(sys);
int qi = getQ(q_sys ? getSys(q_sys) : sysi, q, qid);
add(OP_WAIT_EMPTY, FL_HW | f, 0, getSm(sysi, sm, frame), qi, count);
}
public:
CPA(Params *p);
void startup();
uint64_t getFrame(ThreadContext *tc);
static bool available() { return true; }
bool
enabled()
{
if (!this)
return false;
return _enabled;
}
void dump(bool all);
void dumpKey();
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // !CP_ANNOTATE
#endif //__BASE__CP_ANNOTATE_HH__

9
src/cpu/o3/commit_impl.hh
View File

@@ -46,7 +46,6 @@
#include <string>
#include "arch/utility.hh"
#include "base/cp_annotate.hh"
#include "base/loader/symtab.hh"
#include "base/logging.hh"
#include "config/the_isa.hh"
@@ -1280,14 +1279,6 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
updateComInstStats(head_inst);
if (FullSystem) {
if (CPA::available()) {
if (head_inst->isControl()) {
ThreadContext *tc = thread[tid]->getTC();
CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
}
}
}
DPRINTF(Commit,
"[tid:%i] [sn:%llu] Committing instruction with PC %s\n",
tid, head_inst->seqNum, head_inst->pcState());

1
src/cpu/o3/dyn_inst_impl.hh
View File

@@ -41,7 +41,6 @@
#ifndef __CPU_O3_DYN_INST_IMPL_HH__
#define __CPU_O3_DYN_INST_IMPL_HH__
#include "base/cp_annotate.hh"
#include "cpu/o3/dyn_inst.hh"
#include "debug/O3PipeView.hh"

5
src/cpu/simple/base.cc
View File

@@ -42,7 +42,6 @@
#include "cpu/simple/base.hh"
#include "arch/utility.hh"
#include "base/cp_annotate.hh"
#include "base/cprintf.hh"
#include "base/inifile.hh"
#include "base/loader/symtab.hh"
@@ -586,10 +585,6 @@ BaseSimpleCPU::postExecute()
++t_info.numLoad;
}
if (CPA::available()) {
CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
}
if (curStaticInst->isControl()) {
++t_info.numBranches;
}

124
src/dev/net/i8254xGBe.cc
View File

@@ -56,7 +56,7 @@ using namespace iGbReg;
using namespace Net;
IGbE::IGbE(const Params *p)
: EtherDevice(p), etherInt(NULL), cpa(NULL),
: EtherDevice(p), etherInt(NULL),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), inTick(false),
rxTick(false), txTick(false), txFifoTick(false), rxDmaPacket(false),
pktOffset(0), fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
@@ -133,7 +133,6 @@ IGbE::~IGbE()
void
IGbE::init()
{
cpa = CPA::cpa();
PciDevice::init();
}
@@ -889,19 +888,13 @@ IGbE::DescCache<T>::writeback(Addr aMask)
DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb);
if (max_to_wb <= 0) {
if (usedCache.size())
igbe->anBegin(annSmWb, "Wait Alignment", CPA::FL_WAIT);
else
igbe->anWe(annSmWb, annUsedCacheQ);
if (max_to_wb <= 0)
return;
}
wbOut = max_to_wb;
assert(!wbDelayEvent.scheduled());
igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
igbe->anBegin(annSmWb, "Prepare Writeback Desc");
}
template<class T>
@@ -919,14 +912,9 @@ IGbE::DescCache<T>::writeback1()
for (int x = 0; x < wbOut; x++) {
assert(usedCache.size());
memcpy(&wbBuf[x], usedCache[x], sizeof(T));
igbe->anPq(annSmWb, annUsedCacheQ);
igbe->anPq(annSmWb, annDescQ);
igbe->anQ(annSmWb, annUsedDescQ);
}
igbe->anBegin(annSmWb, "Writeback Desc DMA");
assert(wbOut);
igbe->dmaWrite(pciToDma(descBase() + descHead() * sizeof(T)),
wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf,
@@ -953,18 +941,6 @@ IGbE::DescCache<T>::fetchDescriptors()
size_t free_cache = size - usedCache.size() - unusedCache.size();
if (!max_to_fetch)
igbe->anWe(annSmFetch, annUnusedDescQ);
else
igbe->anPq(annSmFetch, annUnusedDescQ, max_to_fetch);
if (max_to_fetch) {
if (!free_cache)
igbe->anWf(annSmFetch, annDescQ);
else
igbe->anRq(annSmFetch, annDescQ, free_cache);
}
max_to_fetch = std::min(max_to_fetch, free_cache);
@@ -982,7 +958,6 @@ IGbE::DescCache<T>::fetchDescriptors()
assert(!fetchDelayEvent.scheduled());
igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
igbe->anBegin(annSmFetch, "Prepare Fetch Desc");
}
template<class T>
@@ -995,8 +970,6 @@ IGbE::DescCache<T>::fetchDescriptors1()
return;
}
igbe->anBegin(annSmFetch, "Fetch Desc");
DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n",
descBase() + cachePnt * sizeof(T),
pciToDma(descBase() + cachePnt * sizeof(T)),
@@ -1012,14 +985,10 @@ void
IGbE::DescCache<T>::fetchComplete()
{
T *newDesc;
igbe->anBegin(annSmFetch, "Fetch Complete");
for (int x = 0; x < curFetching; x++) {
newDesc = new T;
memcpy(newDesc, &fetchBuf[x], sizeof(T));
unusedCache.push_back(newDesc);
igbe->anDq(annSmFetch, annUnusedDescQ);
igbe->anQ(annSmFetch, annUnusedCacheQ);
igbe->anQ(annSmFetch, annDescQ);
}
@@ -1037,16 +1006,6 @@ IGbE::DescCache<T>::fetchComplete()
DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n",
oldCp, cachePnt);
if ((descTail() >= cachePnt ? (descTail() - cachePnt) : (descLen() -
cachePnt)) == 0)
{
igbe->anWe(annSmFetch, annUnusedDescQ);
} else if (!(size - usedCache.size() - unusedCache.size())) {
igbe->anWf(annSmFetch, annDescQ);
} else {
igbe->anBegin(annSmFetch, "Wait", CPA::FL_WAIT);
}
enableSm();
igbe->checkDrain();
}
@@ -1056,8 +1015,6 @@ void
IGbE::DescCache<T>::wbComplete()
{
igbe->anBegin(annSmWb, "Finish Writeback");
long curHead = descHead();
#ifndef NDEBUG
long oldHead = curHead;
@@ -1067,9 +1024,6 @@ IGbE::DescCache<T>::wbComplete()
assert(usedCache.size());
delete usedCache[0];
usedCache.pop_front();
igbe->anDq(annSmWb, annUsedCacheQ);
igbe->anDq(annSmWb, annDescQ);
}
curHead += wbOut;
@@ -1092,13 +1046,8 @@ IGbE::DescCache<T>::wbComplete()
writeback(wbAlignment);
}
if (!wbOut) {
if (!wbOut)
igbe->checkDrain();
if (usedCache.size())
igbe->anBegin(annSmWb, "Wait", CPA::FL_WAIT);
else
igbe->anWe(annSmWb, annUsedCacheQ);
}
fetchAfterWb();
}
@@ -1341,8 +1290,6 @@ IGbE::RxDescCache::pktComplete()
RxDesc *desc;
desc = unusedCache.front();
igbe->anBegin("RXS", "Update Desc");
uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
DPRINTF(EthernetDesc, "pktPtr->length: %d bytesCopied: %d "
"stripcrc offset: %d value written: %d %d\n",
@@ -1493,11 +1440,8 @@ IGbE::RxDescCache::pktComplete()
enableSm();
pktDone = true;
igbe->anBegin("RXS", "Done Updating Desc");
DPRINTF(EthernetDesc, "Processing of this descriptor complete\n");
igbe->anDq("RXS", annUnusedCacheQ);
unusedCache.pop_front();
igbe->anQ("RXS", annUsedCacheQ);
usedCache.push_back(desc);
}
@@ -1612,9 +1556,7 @@ IGbE::TxDescCache::processContextDesc()
TxdOp::setDd(desc);
unusedCache.pop_front();
igbe->anDq("TXS", annUnusedCacheQ);
usedCache.push_back(desc);
igbe->anQ("TXS", annUsedCacheQ);
}
if (!unusedCache.size())
@@ -1768,8 +1710,6 @@ IGbE::TxDescCache::pktComplete()
assert(unusedCache.size());
assert(pktPtr);
igbe->anBegin("TXS", "Update Desc");
DPRINTF(EthernetDesc, "DMA of packet complete\n");
@@ -1801,9 +1741,7 @@ IGbE::TxDescCache::pktComplete()
(pktPtr->length < ( tsoMss + tsoHeaderLen) &&
tsoTotalLen != tsoUsedLen && useTso)) {
assert(!useTso || (tsoDescBytesUsed == TxdOp::getLen(desc)));
igbe->anDq("TXS", annUnusedCacheQ);
unusedCache.pop_front();
igbe->anQ("TXS", annUsedCacheQ);
usedCache.push_back(desc);
tsoDescBytesUsed = 0;
@@ -1926,9 +1864,7 @@ IGbE::TxDescCache::pktComplete()
if (!useTso || TxdOp::getLen(desc) == tsoDescBytesUsed) {
DPRINTF(EthernetDesc, "Descriptor Done\n");
igbe->anDq("TXS", annUnusedCacheQ);
unusedCache.pop_front();
igbe->anQ("TXS", annUsedCacheQ);
usedCache.push_back(desc);
tsoDescBytesUsed = 0;
}
@@ -1946,17 +1882,14 @@ IGbE::TxDescCache::pktComplete()
tsoPktHasHeader = false;
if (igbe->regs.txdctl.wthresh() == 0) {
igbe->anBegin("TXS", "Desc Writeback");
DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n");
writeback(0);
} else if (!igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() <=
descInBlock(usedCache.size())) {
DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
igbe->anBegin("TXS", "Desc Writeback");
writeback((igbe->cacheBlockSize()-1)>>4);
} else if (igbe->regs.txdctl.wthresh() <= usedCache.size()) {
DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
igbe->anBegin("TXS", "Desc Writeback");
writeback((igbe->cacheBlockSize()-1)>>4);
}
@@ -2141,7 +2074,6 @@ IGbE::txStateMachine()
// iteration we'll get the rest of the data
if (txPacket && txDescCache.packetAvailable()
&& !txDescCache.packetMultiDesc() && txPacket->length) {
anQ("TXS", "TX FIFO Q");
DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
#ifndef NDEBUG
bool success =
@@ -2150,7 +2082,6 @@ IGbE::txStateMachine()
txFifoTick = true && drainState() != DrainState::Draining;
assert(success);
txPacket = NULL;
anBegin("TXS", "Desc Writeback");
txDescCache.writeback((cacheBlockSize()-1)>>4);
return;
}
@@ -2169,10 +2100,7 @@ IGbE::txStateMachine()
if (!txDescCache.packetWaiting()) {
if (txDescCache.descLeft() == 0) {
postInterrupt(IT_TXQE);
anBegin("TXS", "Desc Writeback");
txDescCache.writeback(0);
anBegin("TXS", "Desc Fetch");
anWe("TXS", txDescCache.annUnusedCacheQ);
txDescCache.fetchDescriptors();
DPRINTF(EthernetSM, "TXS: No descriptors left in ring, forcing "
"writeback stopping ticking and posting TXQE\n");
@@ -2182,15 +2110,12 @@ IGbE::txStateMachine()
if (!(txDescCache.descUnused())) {
anBegin("TXS", "Desc Fetch");
txDescCache.fetchDescriptors();
anWe("TXS", txDescCache.annUnusedCacheQ);
DPRINTF(EthernetSM, "TXS: No descriptors available in cache, "
"fetching and stopping ticking\n");
txTick = false;
return;
}
anPq("TXS", txDescCache.annUnusedCacheQ);
txDescCache.processContextDesc();
@@ -2203,8 +2128,6 @@ IGbE::txStateMachine()
unsigned size = txDescCache.getPacketSize(txPacket);
if (size > 0 && txFifo.avail() > size) {
anRq("TXS", "TX FIFO Q");
anBegin("TXS", "DMA Packet");
DPRINTF(EthernetSM, "TXS: Reserving %d bytes in FIFO and "
"beginning DMA of next packet\n", size);
txFifo.reserve(size);
@@ -2213,10 +2136,8 @@ IGbE::txStateMachine()
DPRINTF(EthernetSM, "TXS: getPacketSize returned: %d\n", size);
DPRINTF(EthernetSM,
"TXS: No packets to get, writing back used descriptors\n");
anBegin("TXS", "Desc Writeback");
txDescCache.writeback(0);
} else {
anWf("TXS", "TX FIFO Q");
DPRINTF(EthernetSM, "TXS: FIFO full, stopping ticking until space "
"available in FIFO\n");
txTick = false;
@@ -2236,12 +2157,10 @@ IGbE::ethRxPkt(EthPacketPtr pkt)
rxPackets++;
DPRINTF(Ethernet, "RxFIFO: Receiving pcakte from wire\n");
anBegin("RXQ", "Wire Recv");
if (!regs.rctl.en()) {
DPRINTF(Ethernet, "RxFIFO: RX not enabled, dropping\n");
anBegin("RXQ", "FIFO Drop", CPA::FL_BAD);
return true;
}
@@ -2256,23 +2175,9 @@ IGbE::ethRxPkt(EthPacketPtr pkt)
if (!rxFifo.push(pkt)) {
DPRINTF(Ethernet, "RxFIFO: Packet won't fit in fifo... dropped\n");
postInterrupt(IT_RXO, true);
anBegin("RXQ", "FIFO Drop", CPA::FL_BAD);
return false;
}
if (CPA::available() && cpa->enabled()) {
assert(sys->numSystemsRunning <= 2);
System *other_sys;
if (sys->systemList[0] == sys)
other_sys = sys->systemList[1];
else
other_sys = sys->systemList[0];
cpa->hwDq(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys);
anQ("RXQ", "RX FIFO Q");
cpa->hwWe(CPA::FL_NONE, sys, macAddr, "RXQ", "WireQ", 0, other_sys);
}
return true;
}
@@ -2306,7 +2211,6 @@ IGbE::rxStateMachine()
rxDescCache.writeback(0);
if (descLeft == 0) {
anBegin("RXS", "Writeback Descriptors");
rxDescCache.writeback(0);
DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
" writeback and stopping ticking\n");
@@ -2319,7 +2223,6 @@ IGbE::rxStateMachine()
if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) {
DPRINTF(EthernetSM,
"RXS: Writing back because WTHRESH >= descUsed\n");
anBegin("RXS", "Writeback Descriptors");
if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4))
rxDescCache.writeback(regs.rxdctl.wthresh()-1);
else
@@ -2331,14 +2234,11 @@ IGbE::rxStateMachine()
regs.rxdctl.hthresh())) {
DPRINTF(EthernetSM, "RXS: Fetching descriptors because "
"descUnused < PTHRESH\n");
anBegin("RXS", "Fetch Descriptors");
rxDescCache.fetchDescriptors();
}
if (rxDescCache.descUnused() == 0) {
anBegin("RXS", "Fetch Descriptors");
rxDescCache.fetchDescriptors();
anWe("RXS", rxDescCache.annUnusedCacheQ);
DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
"fetching descriptors and stopping ticking\n");
rxTick = false;
@@ -2354,25 +2254,19 @@ IGbE::rxStateMachine()
}
if (!rxDescCache.descUnused()) {
anBegin("RXS", "Fetch Descriptors");
rxDescCache.fetchDescriptors();
anWe("RXS", rxDescCache.annUnusedCacheQ);
DPRINTF(EthernetSM, "RXS: No descriptors available in cache, "
"stopping ticking\n");
rxTick = false;
DPRINTF(EthernetSM, "RXS: No descriptors available, fetching\n");
return;
}
anPq("RXS", rxDescCache.annUnusedCacheQ);
if (rxFifo.empty()) {
anWe("RXS", "RX FIFO Q");
DPRINTF(EthernetSM, "RXS: RxFIFO empty, stopping ticking\n");
rxTick = false;
return;
}
anPq("RXS", "RX FIFO Q");
anBegin("RXS", "Get Desc");
EthPacketPtr pkt;
pkt = rxFifo.front();
@@ -2381,17 +2275,14 @@ IGbE::rxStateMachine()
pktOffset = rxDescCache.writePacket(pkt, pktOffset);
DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
if (pktOffset == pkt->length) {
anBegin( "RXS", "FIFO Dequeue");
DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
pktOffset = 0;
anDq("RXS", "RX FIFO Q");
rxFifo.pop();
}
DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
rxTick = false;
rxDmaPacket = true;
anBegin("RXS", "DMA Packet");
}
void
@@ -2399,15 +2290,11 @@ IGbE::txWire()
{
txFifoTick = false;
if (txFifo.empty()) {
anWe("TXQ", "TX FIFO Q");
if (txFifo.empty())
return;
}
anPq("TXQ", "TX FIFO Q");
if (etherInt->sendPacket(txFifo.front())) {
anQ("TXQ", "WireQ");
if (DTRACE(EthernetSM)) {
IpPtr ip(txFifo.front());
if (ip)
@@ -2416,8 +2303,6 @@ IGbE::txWire()
else
DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
}
anDq("TXQ", "TX FIFO Q");
anBegin("TXQ", "Wire Send");
DPRINTF(EthernetSM,
"TxFIFO: Successful transmit, bytes available in fifo: %d\n",
txFifo.avail());
@@ -2460,7 +2345,6 @@ IGbE::tick()
void
IGbE::ethTxDone()
{
anBegin("TXQ", "Send Done");
// restart the tx state machines if they are stopped
// fifo to send another packet
// tx sm to put more data into the fifo

38
src/dev/net/i8254xGBe.hh
View File

@@ -36,7 +36,6 @@
#include <deque>
#include <string>
#include "base/cp_annotate.hh"
#include "base/inet.hh"
#include "debug/EthernetDesc.hh"
#include "debug/EthernetIntr.hh"
@@ -55,7 +54,6 @@ class IGbE : public EtherDevice
{
private:
IGbEInt *etherInt;
CPA *cpa;
// device registers
iGbReg::Regs regs;
@@ -172,42 +170,6 @@ class IGbE : public EtherDevice
*/
void checkDrain();
void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) {
if (cpa)
cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st);
}
void anQ(std::string sm, std::string q) {
if (cpa)
cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
}
void anDq(std::string sm, std::string q) {
if (cpa)
cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
}
void anPq(std::string sm, std::string q, int num = 1) {
if (cpa)
cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
}
void anRq(std::string sm, std::string q, int num = 1) {
if (cpa)
cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
}
void anWe(std::string sm, std::string q) {
if (cpa)
cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
}
void anWf(std::string sm, std::string q) {
if (cpa)
cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
}
template<class T>
class DescCache : public Serializable
{

17
src/dev/pci/copy_engine.cc
View File

@@ -46,7 +46,6 @@
#include <algorithm>
#include "base/cp_annotate.hh"
#include "base/trace.hh"
#include "debug/DMACopyEngine.hh"
#include "debug/Drain.hh"
@@ -449,8 +448,6 @@ CopyEngine::regStats()
void
CopyEngine::CopyEngineChannel::fetchDescriptor(Addr address)
{
anDq();
anBegin("FetchDescriptor");
DPRINTF(DMACopyEngine, "Reading descriptor from at memory location %#x(%#x)\n",
address, ce->pciToDma(address));
assert(address);
@@ -479,8 +476,6 @@ CopyEngine::CopyEngineChannel::fetchDescComplete()
if (inDrain()) return;
writeCompletionStatus();
} else {
anBegin("Idle");
anWait();
busy = false;
nextState = Idle;
inDrain();
@@ -499,7 +494,6 @@ CopyEngine::CopyEngineChannel::fetchDescComplete()
void
CopyEngine::CopyEngineChannel::readCopyBytes()
{
anBegin("ReadCopyBytes");
DPRINTF(DMACopyEngine, "Reading %d bytes from buffer to memory location %#x(%#x)\n",
curDmaDesc->len, curDmaDesc->dest,
ce->pciToDma(curDmaDesc->src));
@@ -520,7 +514,6 @@ CopyEngine::CopyEngineChannel::readCopyBytesComplete()
void
CopyEngine::CopyEngineChannel::writeCopyBytes()
{
anBegin("WriteCopyBytes");
DPRINTF(DMACopyEngine, "Writing %d bytes from buffer to memory location %#x(%#x)\n",
curDmaDesc->len, curDmaDesc->dest,
ce->pciToDma(curDmaDesc->dest));
@@ -541,8 +534,6 @@ CopyEngine::CopyEngineChannel::writeCopyBytesComplete()
cr.status.compl_desc_addr(lastDescriptorAddr >> 6);
completionDataReg = cr.status() | 1;
anQ("DMAUsedDescQ", channelId, 1);
anQ("AppRecvQ", curDmaDesc->user1, curDmaDesc->len);
if (curDmaDesc->command & DESC_CTRL_CP_STS) {
nextState = CompletionWrite;
if (inDrain()) return;
@@ -559,8 +550,6 @@ CopyEngine::CopyEngineChannel::continueProcessing()
busy = false;
if (underReset) {
anBegin("Reset");
anWait();
underReset = false;
refreshNext = false;
busy = false;
@@ -581,15 +570,12 @@ CopyEngine::CopyEngineChannel::continueProcessing()
} else {
inDrain();
nextState = Idle;
anWait();
anBegin("Idle");
}
}
void
CopyEngine::CopyEngineChannel::writeCompletionStatus()
{
anBegin("WriteCompletionStatus");
DPRINTF(DMACopyEngine, "Writing completion status %#x to address %#x(%#x)\n",
completionDataReg, cr.completionAddr,
ce->pciToDma(cr.completionAddr));
@@ -610,7 +596,6 @@ CopyEngine::CopyEngineChannel::writeStatusComplete()
void
CopyEngine::CopyEngineChannel::fetchNextAddr(Addr address)
{
anBegin("FetchNextAddr");
DPRINTF(DMACopyEngine, "Fetching next address...\n");
busy = true;
cePort.dmaAction(MemCmd::ReadReq,
@@ -628,8 +613,6 @@ CopyEngine::CopyEngineChannel::fetchAddrComplete()
DPRINTF(DMACopyEngine, "Got NULL descriptor, nothing more to do\n");
busy = false;
nextState = Idle;
anWait();
anBegin("Idle");
inDrain();
return;
}

31
src/dev/pci/copy_engine.hh
View File

@@ -48,7 +48,6 @@
#include <vector>
#include "base/cp_annotate.hh"
#include "base/statistics.hh"
#include "dev/pci/copy_engine_defs.hh"
#include "dev/pci/device.hh"
@@ -136,36 +135,6 @@ class CopyEngine : public PciDevice
void recvCommand();
bool inDrain();
void restartStateMachine();
inline void anBegin(const char *s)
{
CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
channelId, "CopyEngine", s);
}
inline void anWait()
{
CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
}
inline void anDq()
{
CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
}
inline void anPq()
{
CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
}
inline void anQ(const char * s, uint64_t id, int size = 1)
{
CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
"CopyEngine", s, id, NULL, size);
}
};
private: