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dev,arm: Stop using TheISA in ARM specific files.

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These can use ArmISA since there's no ambiguity about what ISA is being
used with those files.

Change-Id: I02e8ea0ab70215679eb939adaa949400e878b1ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32928
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-08-19 03:03:53 -07:00
parent c0f4489220
commit 8477866a13
3 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/isa/insts/neon64.isa
View File

@@ -46,7 +46,7 @@ let {{
smallFloatTypes = ("uint32_t",)
zeroSveVecRegUpperPartCode = '''
TheISA::ISA::zeroSveVecRegUpperPart(%s,
ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
'''

16
src/arch/arm/isa/templates/sve_mem.isa
View File

@@ -146,7 +146,7 @@ def template SveContigLoadExecute {{
%(op_rd)s;
%(ea_code)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
%(rden_code)s;
@@ -203,7 +203,7 @@ def template SveContigLoadCompleteAcc {{
%(op_decl)s;
%(op_rd)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
if (xc->readMemAccPredicate()) {
@@ -233,7 +233,7 @@ def template SveContigStoreExecute {{
%(op_rd)s;
%(ea_code)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
%(wren_code)s;
@@ -270,7 +270,7 @@ def template SveContigStoreInitiateAcc {{
%(op_rd)s;
%(ea_code)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<MemElemType>();
%(wren_code)s;
@@ -929,7 +929,7 @@ def template SveStructLoadExecute {{
%(op_rd)s;
%(ea_code)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
if (fault == NoFault) {
@@ -984,7 +984,7 @@ def template SveStructLoadCompleteAcc {{
%(op_decl)s;
%(op_rd)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
memcpy(memData.raw_ptr<uint8_t>(), pkt->getPtr<uint8_t>(),
@@ -1017,7 +1017,7 @@ def template SveStructStoreExecute {{
%(op_rd)s;
%(ea_code)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
%(wren_code)s;
@@ -1054,7 +1054,7 @@ def template SveStructStoreInitiateAcc {{
%(op_rd)s;
%(ea_code)s;
TheISA::VecRegContainer memData;
ArmISA::VecRegContainer memData;
auto memDataView = memData.as<Element>();
%(wren_code)s;

2
src/dev/arm/generic_timer.cc
View File

@@ -1273,7 +1273,7 @@ GenericTimerMem::GenericTimerMem(GenericTimerMemParams *const p)
void
GenericTimerMem::validateFrameRange(const AddrRange &range)
{
fatal_if(range.start() % TheISA::PageBytes,
fatal_if(range.start() % ArmISA::PageBytes,
"GenericTimerMem::validateFrameRange: Architecture states each "
"register frame should be in a separate memory page, specified "
"range base address [0x%x] is not compliant\n");