arch: Create a base class for decoders.

This base class doesn't actually hold anything yet, it's just a place to
add shared functionality or interfaces later.

Change-Id: Ia33217bd78b1d1ff3df3b2202095576a4e5d8153
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32897
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/decoder.hh

@@ -46,6 +46,7 @@
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "arch/generic/decode_cache.hh"
+#include "arch/generic/decoder.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
 #include "enums/DecoderFlavor.hh"
@@ -54,7 +55,7 @@ namespace ArmISA
 {
 
 class ISA;
-class Decoder
+class Decoder : public InstDecoder
 {
   protected:
     //The extended machine instruction being generated

src/arch/generic/decoder.hh

@@ -0,0 +1,35 @@
+/*
+ * Copyright 2020 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_GENERIC_DECODER_HH__
+#define __ARCH_GENERIC_DECODER_HH__
+
+class InstDecoder
+{
+};
+
+#endif // __ARCH_DECODER_GENERIC_HH__

src/arch/mips/decoder.hh

@@ -30,6 +30,7 @@
 #define __ARCH_MIPS_DECODER_HH__
 
 #include "arch/generic/decode_cache.hh"
+#include "arch/generic/decoder.hh"
 #include "arch/mips/types.hh"
 #include "base/logging.hh"
 #include "base/types.hh"
@@ -39,7 +40,7 @@ namespace MipsISA
 {
 
 class ISA;
-class Decoder
+class Decoder : public InstDecoder
 {
   protected:
     //The extended machine instruction being generated

src/arch/power/decoder.hh

@@ -30,6 +30,7 @@
 #define __ARCH_POWER_DECODER_HH__
 
 #include "arch/generic/decode_cache.hh"
+#include "arch/generic/decoder.hh"
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
 
@@ -37,7 +38,7 @@ namespace PowerISA
 {
 
 class ISA;
-class Decoder
+class Decoder : public InstDecoder
 {
   protected:
     // The extended machine instruction being generated

src/arch/riscv/decoder.hh

@@ -31,6 +31,7 @@
 #define __ARCH_RISCV_DECODER_HH__
 
 #include "arch/generic/decode_cache.hh"
+#include "arch/generic/decoder.hh"
 #include "arch/riscv/isa_traits.hh"
 #include "arch/riscv/types.hh"
 #include "base/logging.hh"
@@ -42,7 +43,7 @@ namespace RiscvISA
 {
 
 class ISA;
-class Decoder
+class Decoder : public InstDecoder
 {
   private:
     DecodeCache::InstMap<ExtMachInst> instMap;

src/arch/sparc/decoder.hh

@@ -30,6 +30,7 @@
 #define __ARCH_SPARC_DECODER_HH__
 
 #include "arch/generic/decode_cache.hh"
+#include "arch/generic/decoder.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
@@ -38,7 +39,7 @@ namespace SparcISA
 {
 
 class ISA;
-class Decoder
+class Decoder : public InstDecoder
 {
   protected:
     // The extended machine instruction being generated

src/arch/x86/decoder.hh

@@ -33,6 +33,7 @@
 #include <unordered_map>
 #include <vector>
 
+#include "arch/generic/decoder.hh"
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/types.hh"
 #include "base/bitfield.hh"
@@ -47,7 +48,7 @@ namespace X86ISA
 {
 
 class ISA;
-class Decoder
+class Decoder : public InstDecoder
 {
   private:
     //These are defined and documented in decoder_tables.cc