Commit Graph

1160 Commits

Author SHA1 Message Date
Daniel R. Carvalho
9b675ebea8 misc: Add missing compiler.hh include
Add some missing base/compiler.hh includes.

Found by manually checking the files in:
  grep -r --include \*.hh -L \
    '#include "base/compiler.hh"' \
    $(grep -r -l "GEM5_" src/)

And occasionally checking some .cc files through
a similar methodology.

Change-Id: I6b6e27189c627bb76ace73c338486743d469be46
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45459
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-14 10:02:14 +00:00
Gabe Black
02ae343c66 misc: Replace M5_CLASS_VAR_USED with GEM5_CLASS_VAR_USED.
Change-Id: Ibd2230d684f41201b07fa9083881145e36176a68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45241
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
c480558532 misc: Replace M5_UNREACHABLE with GEM5_UNREACHABLE.
Change-Id: Id4cbdb8ae58c1077411e01579ac3a2d72b3b7465
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45238
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
ce6b5e7e33 misc: Replace M5_ATTR_PACKED with GEM5_PACKED.
Change-Id: Ie59071ca1fc81a76267a54ddd2d35dfc4477995d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45234
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
11fe13c311 misc: Replace M5_FALLTHROUGH with GEM5_FALLTHROUGH.
Change-Id: I058f311b6d9c284f745bcc915db72236d05db21b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45233
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-11 20:16:31 +00:00
Gabe Black
fb3befcc6d misc: Replace M5_VAR_USED with GEM5_VAR_USED.
Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Gabe Black
00caced648 dev: Overload swap_bytes, don't specialize the template.
The effect is the same, the rules for overloads are easier to work with
than the rules for templates, and it removes the assumption that
swap_bytes actually is a template.

Also some minor style fixes.

Change-Id: Id9439177185b5269dd89605bbd05b09390a18d40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45285
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-11 20:14:56 +00:00
Gabe Black
d84123e106 scons,misc: Remove the ability to disable some trivial features.
These are HDF5, PNG, FENV, and TUNTAP support, all of which add
capabilities to gem5 which can be ignored if not wanted. It could be
argued that FENV changes behavior because it makes setting the FP
rounding mode work or not as used by SPARC, but since the difference is
trivial and in a niche area, that (along with the other options) doesn't
seem to justify having a top level control in the build system.

Since these are no longer options which say whether to *use* a
particular feature, and are instead flags which say whether we *have* a
particular feature, change their names from USE_* to HAVE_*, to stay
consistent with other variables.

Most of the remaining USE_* flags, KVM, FASTMODEL, SYSTEMC, and
(indirectly) USE_PYTHON, toggle on and off major systems which can have
a significant effect on boot time, or, in the case of FASTMODEL, even
consume external resources which may not be available and which may
break the build.

USE_POSIX_TIMER was also left alone since it selects between two
implementations of some functions. By forcing it to be on or off
depending on the host, we would be forcing some code to be excluded in
either case. That would make that other code impossible to test without
hacking up scons or modifying the host machine.

Change-Id: I0b03f23e65478caefd50cd3516974386e3dbf0db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40964
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-10 23:32:33 +00:00
Gabe Black
41d934cf18 misc: Collapse all uses of DTRACE(x) to Debug::x.
Also mark the DTRACE macro as deprecated.

Change-Id: I99d9a9544b539117b375186e3e425d73d3c5cab7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45009
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-10 20:00:48 +00:00
Gabe Black
072cddd765 base,arch,dev,mem: Always compile DPRINTFs, even if they're disabled.
The code in the body of a DPRINTF will always be compiled, even if it's
disabled. If TRACING_ON is false, the if around it will short circuit to
false without actually running any code to check the specified
condition, and the body of the if will be elided by the compiler as
unreachable code.

This creates a more consistent environment whether TRACING_ON is on or
not, so that variables which are only used in DPRINTF don't have to be
guarded by their own TRACING_ON #ifs at the call site. It also ensures
that the code inside DPRINTF is always checked to be valid code, even if
the DPRINTF itself will never go off. This helps avoid syntax errors,
etc, which aren't found because of the configuration of the build being
tested with.

Change-Id: Ia95ae229ebcd2fc9828f62e87f037f76b9279819
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44988
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-10 07:31:12 +00:00
Gabe Black
d33a693e43 arch,cpu: Rename arch/registers.hh to arch/vecregs.hh.
The only thing still in arch/registers.hh were related to vector
registers. To make it obvious that nothing else should be added, this
change renames the file so that it has the much less generic name
arch/vecregs.hh.

Change-Id: I729697dc576e1978047688d9700dc07ff9b17044
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42686
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-07 19:36:08 +00:00
Matthew Poremba
0209e7dede dev-amdgpu: Add initial AMDGPU device
The initial device contains enough code for the gpufs configuration
scripts to register an amdgpu device that identifies as a Vega 10
(Frontier Edition) device when PCI devices are listed by Linux. It also
contains stubs necessary for adding the MMIO interface to handle driver
initialization.

Using the configuration Linux boots and the device is successfully seen
in lspci. The driver can also begin loading an successfully sends
initial MMIOs and attempts to read the ROM.

Change-Id: I7ad87026876f31f44668e700d5adb639c2c053c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44909
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-05 17:33:22 +00:00
Bobby R. Bruce
2c8bade2c3 arch-gcn3,misc: Fix .fast compilation errors for GCN3_x86
Unused variable errors occurred when compiling gem5.fast with GCC. This
patch fixes this.

Change-Id: Iaca1fb8194c2381c0a4ba5d0ea1fb5b8f2a11829
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44885
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-27 23:26:04 +00:00
Kyle Roarty
529736a7ce gpu-compute, dev-hsa: Fix doorbell for gfx900
gfx9 changed the size of the doorbell, and what the write index
is when the doorbell is rang. --gfx-version flag is used to set
the doorbell size

Change-Id: I48e4e57dc1c80a08133b17cdf3f92533b541f7c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42220
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-24 15:54:15 +00:00
Kyle Roarty
ec6b325382 gpu-compute, dev-hsa: Remove HSADriver, HSADevice
HSADriver/HSADevice were primarily used with GPUCommandProcessor/
GPUComputeDriver. This change merges the classes together to
simplify the inheritance hierarchy, as well as removing any casting.

Change-Id: I670eb9b49a16c8aba17e13fd1d1287d0621c9f48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42219
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-24 15:54:15 +00:00
Michael LeBeane
d019912efa dev-hsa: Fix doorbell mmap for APU
Commit id ef44dc9a removed mmap-based doorbell allocation since dGPUs
use ioctl's instead.  However, APUs still need this to work correctly.
Add that logic back in as well as some new logic to distinguish doorbells
mmaps from other types. Also add some additional commentary regarding
Event page mmaps.

Change-Id: I8507ac85c8f07886d0fb4f95bde5e18a7790eab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42218
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-24 15:54:15 +00:00
Giacomo Travaglini
c2b91143b4 dev-arm: Turn flash1 into a CFI Flash Memory
Change-Id: I21bdc165fba88d6366ea500a8a662fe0dcc02dab
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41496
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-04-16 09:52:55 +00:00
Michael LeBeane
a5f55e0be1 gpu-compute: Topology and driver changes for dGPU
New topology ripped from Fiji to support dGPU.  A dGPU flag is added to
the config which is propogated to the driver.  The emulated driver is
now able to properly deal with dGPU ioctls and mmaps.  For now, dGPU
physical memory is allocated from the host, but this is easy to change
once we get a GPU memory controller up and running.

Change-Id: I594418482b12ec8fb2e4018d8d0371d56f4f51c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42214
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 16:41:11 +00:00
Giacomo Travaglini
921d370135 dev: Fix GCN3_X86 builds on aarch64 host
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ic826f0cb46e07b9b5135eee1e518bc13f3d978a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44485
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-15 08:02:45 +00:00
Gabe Black
960b9246c5 scons: Convert gem5_scons.Configure to a context manager.
This has two purposes. First, SCons assumes that once you call
Configure, you won't set up the environment the Configure is based on
until after you get the environment back from it again with
conf.Finish(). We get away with this when the cache mode for config
tests is not "force", since Configure just reuses the environment we
pass in, and any changes we make are immediately communicated between
the two.

If the cache mode *is* "force" though, SCons modifies the decider so
that everything the conf environment goes to build looks like it's out
of date. It does that by cloning the original environment, and then
using that clone to do its tests. That causes a problem because we have
a long lived "conf" object and make further changes to main, and since
the two environments are now separate the one in conf doesn't see those
updates.

Second, and more subtly, we export our "main" and "env" environments so
that other SConsopts and SConscript files can use them and define things
in them. The way Configure is designed, if the config caching mode is
"force", then it will create a new environment, and then that
environment will replace what the, for instance, "main" variable points
to when "main = conf.Finish()" is executed.

Unfortunately, if we've already Export()-ed main, we've exported what
the "main" variable pointed to at that time. Our view of "main" will
track with the value that conf.Finish() returned, but since that
construction environment is mearly derived from the main we Exported and
not actually the same thing, they have diverged at that point and will
behave independently.

To solve both of these problems, this change modifies the
gem5_scons.Configure() method so that it's a context manager instead of
a regular function. As before, it will call Configure for us and create
a configuration context, which it will yield as the "with" value. When
the context exits, all the variables in the context Finish() returns
will be shoved back into the original context with Replace(). This isn't
perfect since variables which were deleted in the environment (probably
very rare in practice) will not exist and so will not overwrite the
still existent variable in the original dict.

This has several advantages. The environment never splits into two
copies which continue on independently. It makes the lifetime of a
configuration context short, which is good because behavior during that
time is tricky and unintuitive. It also makes the scope of the context
very clear, so that you won't miss the fact that you're in a special
setting and need to pay attention to what environment you're modifying.

Also, this keeps the conceptual overhead of configuration localized to
where the configuration is happening. In parts of the SConscripts which
are not doing anything with conf, etc, they don't have to modify their
behavior since no configuration context is active.

This change is based on this change from Hanhwi Jang who identified this
problem and proposed an initial solution:

https://gem5-review.googlesource.com/c/public/gem5/+/44265

Change-Id: Iae0a292d6b375c5da98619f31392ca1de6216fcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44389
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Hanhwi Jang <jang.hanhwi@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 01:04:54 +00:00
Daniel R. Carvalho
0a80511aea dev: Fix compilation errors
'backing' was initialized after being used.
'buffer' was initialized after its data() was used
by the constructor.

Change-Id: I0f8d0f6efb5d4b7abc5fc6c2c3ecca2c9b0a2eaf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44366
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-12 12:23:34 +00:00
Giacomo Travaglini
b3af12ccd5 dev-arm: Align gem5 to FVP Base PCI
The VExpress_GEM5_Foundation platform was reserving
a region of the memory map (@ 0x4 0000 0000) for PCI.

The Armv8-A FVP Foundation platform is not PCI capable at
the moment, so any PCI logic is really gem5 specific.
With this patch we are aligning gem5 to the FVP Base Platform,
which supports PCI and it is reserving 256GiB of memory
starting at 0x40 0000 0000 (256GiB).

Fast Models - Reference Manual - Version 11.8

At the moment we are still supporting a single DRAM range,
starting at 2GiB. So DRAM could overlap with the PCI memory
region though it is unlikely to happen in near future as
it would require a DRAM size > 254 GiB.

JIRA: https://gem5.atlassian.net/browse/GEM5-898

Change-Id: I506fd6696cdddc39d057602581cb16b30db3f7c7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44165
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-04-07 09:09:49 +00:00
Daniel R. Carvalho
5c8983fc18 misc: Fix remaining opening braces
These were not caught by the previous patches because
the grep used ignored:
- anonymous structures
  (e.g., "struct {")
- opening braces without leading spaces
  (e.g., "struct Name{"),
- weird chars in auto-generation files
  (e.g., "struct $name {").
- extra characters after the opening brace.
  (e.g., "struct Name { // Comment")
- typedefs (note that this is not caught by the verifier)
  (e.g., "typedef struct Name {")

Most of this has been fixed be grepping structures
with the following regex:
  grep -nrE --exclude-dir=systemc \
    "^ *(typedef)* *(struct|class|enum|union) [^{]*{$" src/

The following makes sure that "struct{" is captured:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union){" src/

To find cases that contain a comment after the
opening brace:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union)[^{]*{\s*//" src/

Change-Id: I9f822bed628d13b1a09ccd6059373aff63a8d7bd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-07 01:29:31 +00:00
Kyle Roarty
c734ab7602 dev-hsa,gpu-compute: Fix override for updateHsaSignal
Change 965ad12 removed a parameter from the updateHsaSignal
function. Change 25e8a14 added the parameter back, but only for the
derived class, breaking the override. This patch adds that parameter
back to the base class, fixing the override.

Change-Id: Id1e96e29ca4be7f3ce244bac83a112e3250812d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44046
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-03 02:39:27 +00:00
Gabe Black
1791b8732c scons: Pull domain specific build setup out of SConstruct.
Use SConsopts files local to individual domains to pull
non-foundational build code out of SConstruct. This greatly simplifies
SConstruct, and also makes it easier to find build configuration having
to do with particular pieces of gem5.

This change also converts some python level variables, all_protocols,
protocol_dirs, and slicc_includes, into the environment where the timing
of their initialization is more flexible.

Change-Id: Ie61ceb75ae9e5557cc400603c972a9582e99c1ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40872
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-04-03 01:18:17 +00:00
Gabe Black
8866d766ad dev,arch-x86: Simplify the relationship between the PC and SouthBridge.
The SouthBridge used to have a parameter to point back at a Platform
object which it would dynamically cast to the Pc platform type, and it
would use that to tell the Pc platform where it was. The Pc platform
would then configure initial values in the SouthBridge during the init
phase. Now, the Pc platform has a parameter which by default
instantiates a SouthBridge, so that it will have a pointer
automatically. The Pc object knows it will have a SouthBridge, and now
the SouthBridge no longer has to assume that it's housed inside a Pc
platform.

Also, the SouthBridge device had instantiated a lot of child objects,
and then to ensure that they were accessible in c++, they were also set
as parameters on the object. Now, these children are created as the
default value for those parameters. They no longer have to be declared
and then separately hooked up as parameters. They could also
theoretically be replaced more easily since they're now only defaults,
although in practice that's unlikely.

Change-Id: I296b18a55ab6aedbb609ca4f545f7b19c21fd905
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43886
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-31 20:56:34 +00:00
Gabe Black
f201a95e2a dev: Fix style in the south bridge device.
Change-Id: I0d5b027c7ef18491147d7bd9d34db33edd438ca0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43885
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-03-30 21:56:51 +00:00
Gabe Black
3f67faec83 arch,dev,gpu-compute,sim: Rename isa_traits.hh page_size.hh.
The only thing left in isa_traits.hh are two constants, one for the
number of bytes in a page, and one for how far to shift an address to
get the page number. To make it clear that this is the only thing
isa_traits.hh should be used for from this point forward (until it is
entirely eliminated), this change renames it to the much less generic
page_size.hh.

Also, because isa_traits.hh used to have *much* more stuff in it, it was
included in a lot of places it didn't need to be. This change also
clears out all these legacy includes while updating the actually needed
ones to the new name.

Change-Id: I939b01b117c53d620b6b0a98982f6f21dc2ada72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40179
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-30 10:17:48 +00:00
Gabe Black
26c62ae563 dev: Remove cruft from the Platform devices.
These bits of cruft are unnecessary includes, unnecessary declarations
of classes which aren't used, and methods which aren't used, and are
also frequently not implemented.

Change-Id: I3df6d60983354bb545bc11880fb6e16fe74adb1d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43665
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-29 21:10:30 +00:00
Gabe Black
5f95d7a89a dev,cpu,configs: Get rid of the IntrControl device.
This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.

Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-29 20:54:16 +00:00
Bobby R. Bruce
a68adcfad5 Merge "misc: Merge branch v21.0.0.0 into develop" into develop 2021-03-26 18:21:34 +00:00
Bobby R. Bruce
502ad193ae misc: Merge branch v21.0.0.0 into develop
This incorporates the last of the v21.0 staging branch changes into the
develop branch.

Change-Id: I89349ac5c52fd454eb87d6199ea5ccde0d50dda3
2021-03-25 14:42:27 -07:00
Daniel R. Carvalho
a362ca93b7 dev-hsa: Fix includes
Partial fix of includes of the files in src/dev/hsa.
It is a partial fix because there might still be
some transitive dependencies - i.e., this process
was not automated.

Change-Id: Ib2f197fc7c97ed1c828c99b2584693cf03b31361
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43585
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-25 21:02:21 +00:00
Kyle Roarty
8f577e6e23 dev-hsa: Fix size of HSA Queue
In the HSAQueueDescriptor ptr function, we mod the index by numElts, but
numElts was previously just set to size, which was the raw size of the
queue. This lead to indexing past the queue. We fix this by dividing by
the size by the AQL packet size to get the actual number of elements the
queue can hold.

We also add an assert for indexing into the queue, as there is a
scenario where the queue reports a larger size than it actually is.

Change-Id: Ie5e699379f303255305c279e58a34dc783df86a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42423
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-25 16:34:16 +00:00
Peter
451cb4cb7a arch-riscv: Fix Clint and SATP write side effects
Previously, RISC-V FS support was unable to support O3CPU.
It was due to two issues:

1. CLINT was calling tc->setMiscRegNoEffect which triggers
a conditionalSquash on O3CPU. These frequent squashes led
to assertion error in src/cpu/o3/inst_queue_impl.hh line
1293 (we still suspect that the assertion might contain
some assumptions).

2. A CSR write to SATP needs to trigger a squash (since
MMU can be activated). This is done by conditionally
adding the IsSquashAfter flag to CSR operations if the
target is SATP. This is a simple fix. (Else, an auipc
right after a CSR write to SATP might compute the wrong
value). In the future, a better implementation should
only set the flag for writes to the relevant bit(s).

Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43244
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Peter Yuen <petery.hin@huawei.com>
2021-03-24 02:48:14 +00:00
Peter Yuen
39108150ab arch-riscv: Added DTB Generation Functionality to RISC-V FS
Changes:
1. RiscvBareMetal
The RiscvBareMetal class and API are preserved for backwards
compatibility, but the base class RiscvFSWorkload is removed
as it inherits from the Workload class. However, most needed
functionalities are already implemented in the KernelWorkload
class

2. RiscvLinux
The RiscvLinux class is added. A dtb filename can be specified
to be loaded to the corresponding memory address.

3. HiFive, Clint, Plic, Uart8250, VirtIOMMIO
Devicetree node generation function is added.

4. tlb, faults
Unnecessary includes of arch/riscv/fs_workload are removed.

Change-Id: Ia239b5614bd93d8e794330ead266f6121a4d13cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42053
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-03-24 02:47:30 +00:00
Daniel R. Carvalho
b2c0b191e1 misc: Fix coding style for union's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *union [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>union X ... {

by:

    <indent level>union X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^union ([A-Za-z].*) \{$/union \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    union ([A-Za-z].*) \{$/    union \1\n    \{/g'

and so on.

Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43328
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-03-23 16:26:04 +00:00
Daniel R. Carvalho
7f1de4e686 misc: Fix coding style for enum's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-23 16:26:04 +00:00
Bobby R. Bruce
af81ec9041 Merge "misc: Merge branch 'release-staging-v21-0' into develop" into develop 2021-03-19 21:13:58 +00:00
Daniel R. Carvalho
2922f763e1 misc: Fix coding style for struct's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Daniel R. Carvalho
469f0671d1 misc: Fix coding style for class-opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *class [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>class X ... {

by:

<indent level>class X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^class ([A-Za-z].*) \{$/class \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    class ([A-Za-z].*) \{$/    class \1\n    \{/g'

and so on.

Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Bobby R. Bruce
68064d8043 misc: Merge branch 'release-staging-v21-0' into develop
Change-Id: I0ad043ded56fb848e045057a1e7a56ea39797906
2021-03-18 11:13:14 -07:00
Gabe Black
c0317722ec dev: Clean up the VirtIO9PDiod::startDiod method.
Rather than print the errno, print the result of strerror so the user
doesn't have to look up what each error code does. Don't duplicate
descriptors needlessly which have been returned by pipe(). Use panic_if
instead of if () panic. Check each call to a standard library function
instead of calling multiple and then only knowing that one of them
failed (but not which one). Close the far side of our pipes for both
the gem5 process, and the process that will become diod. Remove some
stray #undef-s which undefine macros that were never defined. Don't
try to force the descriptors going to diod to be particular numbers.
Slightly reduce nesting in the if which checks the results of fork.
Drop unnecessary \n-s in calls to panic, inform, etc. Minor spacing
related style fixes. Use nullptr instead of NULL.

Change-Id: I48d93778a1e139ef624876a0b316486aac774d7f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43083
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:46:53 +00:00
Giacomo Travaglini
9ffcf15471 dev-arm: Remove unused SMMUv3 WalkCache variables
Those were grouped within the stats data structures but were
not actually stats

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I01bbbada423825ded04a033c0709108e2980ec70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42985
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00
Giacomo Travaglini
d8b172917a dev-arm: Fix WalkCache stats
The WalkCache stats are wrongly using the legacy framework.
With this patch we are registering those to the hierarchical structure.

As we need to pass the Stats::Group parent at construction time,
we are replacing 2d arrays with Vector2d for count stats and using a flat
vector of pointers for the Formula stats

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I8992bc262a376e4e81a4d608c11dff6902e0a01d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42984
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00
Giacomo Travaglini
1806525833 dev-arm: Fix SMMUv3BaseCache Stats
After [1] the SMMUv3BaseCache stats are undistinguible within each
other.

With this patch we are adding a string to their constructor so
that we can distinguish between an IPA, Config etc cache stat

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/36415

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iaa84ed948cf2a4c36ea4fcda589676b9bbeed6fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42983
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00
Peter Yuen
975fcf1355 arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU
Added takeover methods for PMA Checker and RiscvTLB to ensure
that checkpoint restoration works. Also added logic in PLIC
to prevent posting interrupts to a CPU that has yet to complete
the current interrupt. PLIC's behaviour when a CPU claims another
interrupt before completion is also changed. Now PLIC will return
the uncompleted interrupt ID instead of return 0. This behaviour
is not documented in the specs but is designed this way to avoid
issues from CPU side (especially MinorCPU).

Change-Id: I68eaaf56d2c4d76cc1e0a1e2160f5abe184c2cd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41933
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
2021-03-13 08:06:29 +00:00
Gabe Black
e837fdc65c base,misc: Collapse and eliminate the ULL and LL macros.
These just move the ULL or LL suffix to the value in question, and cast
to a uint64_t or an int64_t. We should be able to drop the cast
entirely, and turn the macro into a suffix for the literals in question.

Change-Id: Ia3db35d56137b57def6cf8e27e8457357eb83f62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-11 04:14:17 +00:00
Gabe Black
4dcfa34c18 arch-arm,base,dev: Eliminate the power() function from intmath.hh.
This function causes problems with gcc 5 which incorrectly complains
about the call to warn_if inside a constexpr function. That should only
be an error if a call to a non-constexpr is unavoidable, and even then
the compiler isn't required to emit a diagnostic.

Rather than drop the warning, or add ifdefs to deal with these defective
versions of gcc, this change eliminates the power() function entirely.
Most inputs to this function would overflow anyway, which is reportedly
why no integer version of an exponentiation function is defined in the
standard library, and all uses of this function can easily and more
efficiently be replaced by simple left and right shifts.

Finally, by eliminating the power() function, we also remove the
dependence on base/logging.hh.

Change-Id: I4d014163883d12db46da4ee752696c8225534ee8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42504
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-09 09:09:45 +00:00
Gabe Black
36b57f9b4e arch-sparc: Fix an operator precedence bug in the iob device.
Like in the nomali library, this bug is in some code making a bitmask
where what bits are enabled depends on some conditions. It used ?: to
evaluate the conditions and | to aggregate the bits, but didn't use any
()s, so the | happened first, then the ?:s. This would generate an
incorrect bitmask.

Change-Id: Iabcc8a9fd38cde5de3c0627a3b143407247c0c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40955
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
2021-03-06 05:47:39 +00:00