Commit Graph

15467 Commits

Author SHA1 Message Date
Matt Sinclair
8177fc4392 arch-gcn3: add support for unaligned accesses
Previously, with HSAIL, we were guaranteed by the HSA specification
that the GPU will never issue unaligned accesses.  However, now
that we are directly running GCN this is no longer true.
Accordingly, this commit adds support for unaligned accesses.
Moreover, to reduce the replication of nearly identical
code for the different request types, I also added new helper
functions that are called by all the different memory request
producing instruction types in op_encodings.hh.

Adding support for unaligned instructions requires changing
the statusBitVector used to track the status of the memory
requests for each lane from a bit per lane to an int per lane.
This is necessary because an unaligned access may span multiple
cache lines.  In the worst case, each lane may span multiple
cache lines.  There are corresponding changes in the files that
use the statusBitVector.

Change-Id: I319bf2f0f644083e98ca546d2bfe68cf87a5f967
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29920
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 20:41:18 +00:00
Xianwei Zhang
fbcdf880ee arch-gcn3: Implement instruction v_div_scale_f32
Instruction v_div_scale_f32 was unimplemented, the
implementation was added by mimicking v_div_scale_f64.

Change-Id: I89cdfd02ab01b5936de0e9f6c41e7f3fc4f10ae1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29919
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 20:40:58 +00:00
Xianwei Zhang
f552ab85cb config: fix settings of kernel boundary sync flags
Change-Id: I58a8edc5d324bdcaa84e3d715e2712a43e8ede0d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29918
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 20:40:42 +00:00
Xianwei Zhang
2c1e9c4e81 gpu-compute: enable flexible control of kernel boundary syncs
Kernel end release was turned on for VIPER protocol, which
is in fact write-through based and thus no need to have
release operation. This changeset splits the option
'impl_kern_boundary_sync' into 'impl_kern_launch_acq'
and 'impl_kern_end_rel', and turns off release on VIPER.

Change-Id: I5490019b6765a25bd801cc78fb7445b90eb02a3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29917
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 20:40:05 +00:00
Matthew Poremba
eb9efdaa44 gpu-compute: remove recvToken from GM pipe exec
Tokens were previously acquired in GM pipe exec but has been moved to
acqCoalescerToken. This removes the extraneous code which was acquiring
tokens twice, causing them to be depleted and triggering an assertion.

Change-Id: Ic92de8f06cc85828b29c69790bdadde057ef1777
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29916
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 20:35:11 +00:00
Tony Gutierrez
b811d3a342 mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
This change adds DMA support to the MOESI_AMD_Base-dir.sm,
which is needed to support ROCm apps/GCN3 ISA in the VIPER
ptl. The DMA controller is copied from the MOESI_hammer-dma.sm
with few modifications.

Change-Id: I56141436eee1c8f62c2a0915fa3b63b83bbcbc9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29914
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 20:34:06 +00:00
Tuan Ta
18ebe62598 mem-ruby: GCN3 and VIPER integration
This patch modifies the Coalescer and VIPER protocol to support memory
synchronization requests and write-completion responses that are
required by upcoming GCN3 implementation.

VIPER protocol is simplified to be a solely write-through protocol.

Change-Id: Iccfa3d749a0301172a1cc567c59609bb548dace6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29913
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 20:32:54 +00:00
Matthew Poremba
3ca404da17 sim: Initialize stackSize and stackMin in MemState
Initialize _stackSize and _stackMin to the maximum stack size values.
The are setup in each arch's Process::initState and may be uninitialized
until then. If a stack fixup occurs before these are setup, addresses
which are not in the stack might be allocated on the stack. This
prevents that until they are initialized in Process::initState. If an
access occurs before that with these initial values, the stack fixup
will simply allocate a page of memory in the stack space. However, it
will not print the typical info messages about growing the stack during
this time.

Change-Id: I9f9316734f4bf1f773fc538922e83b867731c684
JIRA: https://gem5.atlassian.net/browse/GEM5-629
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30394
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 14:19:36 +00:00
Michiel W. van Tol
562498f6c4 arch-arm: Add missing isFirstMicroop flags on uop sequences
Certain micro-op sequences were only setting isLastMicroop flags,
and did not set the isFirstMicroop flag. This adds the missing
setFirstMicroop() calls. This fixes tracing issues (e.g. Tarmac)
of certain micro-opped instruction sequences such as LD1.

Change-Id: I7de3ee2759e2b4e1065a7cbac4186f11227d84be
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30034
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-19 09:16:25 +00:00
Gabe Black
cfdf185a15 cpu: Remove default argument values for the update() method in bpreds.
These defaults are never used. There was an assert in the predictors
until recently which was asserting that one of the arguments didn't
have the default value, I think to verify that the default wasn't used
by accident(?), but it could be used purposefully. That would cause
gem5 to crash and has been removed.

Beyond that, there's no reason to have default values for those
arguments in the first place, so this change removes them. That makes
the code slightly simpler, and avoids them being used by accident.

Additionally, the defalt values of the arguments made the function
signatures inconsistent, even though they were supposed to override
each other.

JIRA: https://gem5.atlassian.net/browse/GEM5-483

Change-Id: I28f8d2048985c12ec9cac018a868a32bfa20dc6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30375
Reviewed-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-18 22:38:52 +00:00
Giacomo Travaglini
19f936492c ext: Remove dead code from runner.py
This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Ic851c3681a40b7e61ee53b81b17df52dc1289e9f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30240
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 15:07:47 +00:00
Giacomo Travaglini
f7d15b9c05 ext: Remove dead code from handlers.py
This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: If878ea1900e2bcd76646b9860f2cc3f808bc5082
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30239
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 15:07:47 +00:00
Giacomo Travaglini
002fb0b1d2 ext: Remove dead code from fixture.py
This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Ifa55a846ba22a84a0f684ffbf870506af7c1045c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30238
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 15:07:47 +00:00
Giacomo Travaglini
06b6767bbe ext: Remove dead code from loader.py
This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I4193eff3ea4194f793547767a47c3ac5a64813fd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30236
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
7864b174bc ext: Remove dead code from helper.py
This has been tested with vulture:
https://pypi.org/project/vulture/

Change-Id: I32aad410145dd142bba8e0b9ab912e9c2bad6001
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30235
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
0fb60e91f8 ext: Remove dead code from test_util.py
JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I722185e890e25ad04271b476c4d1ffa722cade62
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30216
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
d864b67dc3 ext: Remove LogWrapper/TestLogWrapper from log.py
This patch is removing:

* LogWrapper (wrapping Log)
* TestLogWrapper (wrapping LogWrapper)

There is now a single Log class to be used for logging

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I038298565e2ccbe448664a538f888c96fdce8f4a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30234
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
3e09b8eb02 ext: Fix the MakeFixture setup
It was simply using an invalid log_call helper

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I644b1c902a81a27beb6385690d2e43baf4c0919b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30218
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
60453334e3 ext: Avoid specifying empty interfaces and embrace duck typing
It turns out no handler is implementing

prehandle()
posthandle()

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Ie8d92027f29fc33192fcf0d495fd3c4f6e4075aa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30217
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
2e26b4a474 ext: Remove sandbox module from testlib
The sandbox module is providing a sandbox environment for
a specific TestCase via the multiprocessing package.

This isolation/complexity is not strictly needed as testlib is already
forking a new process via subprocess. As it is now, a TestRunner will
generate:

TestRunner -> multiprocessing.Process -> subprocess.Popen
(2 generated procs)

With this patch we are removing the intermediate layer

TestRunner -> subprocess.Popen
(1 generated proc)

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Icd5cadbe316653a9269ab098ec4c07f21b864ad3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30215
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Giacomo Travaglini
8c0d063e37 tests: log_call is not returning any value
JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I2713ddacc762d614e3992718ea234287d06c179a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30214
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2020-06-18 14:28:14 +00:00
Gabe Black
6b18ec642e mem: fixupAddr should not panic if it fails.
This function should just return false in that case, and its callers
should figure out what to do. Otherwise, when calling tryReadBlob in SE
mode, a failure to read the blob makes gem5 panic instead of just
returning false.

Change-Id: I74b9cb98f595c52300d683842ece68c6031d9b85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30376
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-18 03:58:48 +00:00
Gabe Black
187ba10c92 arch,cpu,sim: Eliminate the now empty kernel statistics classes.
This includes the base and ISA specific Kernel::Statistics classes, the
plumbing through ThreadContext to access them, and the switching
header file associated with them.

Change-Id: Ia511a59325b629aa9ccc0e695ddd47ff11916499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25149
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 19:54:41 +00:00
Gabe Black
44f787ae97 arch,kern,sim: Move the stats in Kernel::Statistics to Workload.
These are the stats in the base class, not in any derived classes. Only
Alpha has an additional stats. These were not really "kernel"
statistics, they were just applicable primarily in FS. They are
potentially applicable to any simulation, but will probably not be
incremented in SE simulations.

Also this merges these stats from being per thread to being per
workload, ie operating system instance. This is probably more relevant
since exactly what thread within a workload runs which particular
instruction is not very important/predictable, but the aggregate
behavior is. If necessary, this could be adjusted in the future to
split things back out again into stats per thread while keeping them
inside the single workload object.

Change-Id: I130e11a9022bdfcadcfb02c7995871503114cd53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25147
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 19:54:13 +00:00
Tony Gutierrez
9d51dec937 arch, gpu-compute: Remove HSAIL related files
Change-Id: Iefba0a38d62da7598bbfe3fe6ff46454d35144b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28410
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-17 02:53:47 +00:00
Gabe Black
d2beb1ffc8 mem: Use the new unbound port reporting mechanism in the mem ports.
There was an add-hoc check added to getAddrRanges, but the other methods
would just segfault if they tried to talk to their peers. This change
wraps all the calls in try blocks and catches the exception which the
peer will throw if it's the default and the port is not actually
connected to anything.

Change-Id: Ie46be0230f33f74305c599b251ca319a65ba008d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30296
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 20:15:12 +00:00
Nikos Nikoleris
35d9bf99a8 mem: Fix latency handling in MemDelay
MemDelay wouldn't consume pre-existing delays in the packet and
therefore the latency it adds would overlap with them. This patch
fixes the MemDelay to properly account for them.

Change-Id: I7330fbf1c8161a21523a0b4aab31c72e34bce650
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30055
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 16:13:43 +00:00
Gabe Black
d3024accaf sim: Add some helpers to catch and reporting using unbound ports.
If a port is unbound, trying to call its peer will likely cause a
segfault. Rather than check if a port is bound every time you go to use
it, we can instead bind to a default peer which just throws an exception
back to the caller. The caller can catch the exception and report the
error.

This change adds a common new class to throw as the exception, and also
a small utility function which reports the error and dies.

Change-Id: Ia58a2030922c73e2fd7d139822bce38d9b0f2171
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30295
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-16 02:35:41 +00:00
Gabe Black
5d80780f89 arm: Add missing overrides to the ARM interrupt object.
Change-Id: Idddc5267d5eb287a0895a1a2e1631ca9a2e789f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30294
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 23:31:15 +00:00
Tony Gutierrez
b8da9abba7 gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU model
Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29912
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 22:45:17 +00:00
Daniel R. Carvalho
b0eac7857a base: Delete deletePointer helpers
Now that the calls to deletePointer have been replaced by the use
of smart pointers, they can be safely removed.

Change-Id: I91d8b97f7ba3f64dd9948fd343cf0af969886598
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24251
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 19:52:54 +00:00
Nikos Nikoleris
6a4b69c4fd mem: Add a header latency parameter to the XBar
The XBar uses the concept of Layers to model throughput and
instantiates one Layer per master. As it forwards a packet to and from
master, the corresponding Layer is marked as occupied for a number of
cycles. Requests/responses to/from a master are blocked while the
corresponding Layer is occupied. Previously the delay would be
calculated based on the formula 1 + size / width, which assumes that
the Layer is always occupied for 1 cycle while processing the packet
header. This changes makes the header latency a parameter which
defaults to 1.

Change-Id: I12752ab4415617a94fbd8379bcd2ae8982f91fd8
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30054
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-15 12:57:52 +00:00
Giacomo Travaglini
ceb93d2182 tests: Use default None argument in makeArmSystem
JIRA: https://gem5.atlassian.net/browse/GEM5-387

Change-Id: I18b1ed360b2d285e4df19b896e692356ef6f8819
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30219
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
2020-06-14 19:26:40 +00:00
Gabe Black
d45c4b7523 scons: Fix how partial linking is disabled.
Setting disable_partial part way through the checks for various build
targets is incorrect and will affect targets based on the order they're
checked.

This change moves the check earlier, makes it consistent across all
builds whether fast is included or not, and stops passing it in as an
option to makeEnv since it now applies universally.

By disabling partial linking consistently, we avoid missing bugs where
only the "fast" version of gem5 doesn't build correctly because of the
multitude of g++ bugs having to do with combining LTO and partial
linking.

This also simplifies the logic in the SConscript by having fewer
independently moving parts.

Change-Id: Iff69f39868e948d3b9a5b11ea80bbfed19419b59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29303
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-06-12 08:48:14 +00:00
Gabe Black
1008b70f31 mem-ruby: Add a missing override.
Change-Id: I7651ca0f4658ddd49cfd13d9d5f7e430f416f41f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30254
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-12 06:23:23 +00:00
Gabe Black
260fc34c97 arch,cpu: Add a setThreadContext method to the ISA class.
Also remove ThreadContext pointer parameters to some of the methods in
the ISA classes.

Change-Id: I8e502b1857d299cb2e759a9734a1df4f65f31efe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29233
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-12 05:41:41 +00:00
Gabe Black
bd9fb89122 arch,cpu: Change setCPU to setThreadContext in Interrupts.
The ThreadContext can be used to access the cpu if needed, and is a
more representative interface to various pieces of state than the CPU
itself. Also convert some of the methods in Interupts to use the
locally stored ThreadContext pointer instead of taking one as an
argument. This makes calling those methods simpler and less error
prone.

Change-Id: I740bd99f92e54e052a618a4ae2927ea1c4ece193
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28988
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-11 23:42:54 +00:00
Kyle Roarty
432ecdfbdc sim-se: Ignore unimplemented system call
System call sched_setaffinity causes crashes when running programs
that use ROCm. Ignoring the system call allows for the programs
to run to completion.

Change-Id: I27c767ef81091789e228d47f2bb5f6fa18f11539
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30154
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-11 21:00:12 +00:00
Gabe Black
9757529064 sim: Delete an unused member in the System class.
This was supposed to be deleted as part of the change titled:
arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.

but it was left out of the checked in version somehow.

Change-Id: I0dbb0b4fa6ae29649a80d1cb883e48ad50116c31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30194
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-11 03:00:33 +00:00
Bobby R. Bruce
c1bf5469d8 misc: Reverted version information to "develop"
Change-Id: I6ee1bae48f2dd0d868dfbb428e93deeb9ee93083
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29833
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-10 20:46:52 +00:00
Gabe Black
0dfa59f0bb arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.
The System class has a few different arrays of values which each
correspond to a thread of execution based on their position. This
change collects them together into a single class to make managing them
easier and less error prone. It also collects methods for manipulating
those threads as an API for that class.

This class acts as a collection point for thread based state which the
System class can look into to get at all its state. It also acts as an
interface for interacting with threads for other classes. This forces
external consumers to use the API instead of accessing the individual
arrays which improves consistency.

Change-Id: Idc4575c5a0b56fe75f5c497809ad91c22bfe26cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25144
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 23:37:29 +00:00
Gabe Black
5da62e6331 arch,base,cpu,kerm,sim: Build a symbol table for object files.
Instead of calling into object files after the fact and asking them to
put symbols into a target symbol table, this change makes object files
fill in a symbol table themselves at construction. Then, that table can
be retrieved and used to fill in aggregate tables, masked, moved,
and/or filtered to have only one type of symbol binding.

This simplifies the symbol management API of the object file types
significantly, and makes it easier to deal with symbol tables alongside
binaries in the FS workload classes.

Change-Id: Ic9006ca432033d72589867c93d9c5f8a1d87f73c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24787
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 23:37:29 +00:00
Xianwei Zhang
7f4d6c8388 mem-ruby: Add codes for pure virtual functions for compilation
Change-Id: Ic34f9ccf10ec28d68eed236dc6246e2ae2ef1b89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28409
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2020-06-09 20:00:13 +00:00
Tuan Ta
adc9de4d61 mem-ruby: update memory interfaces to support GPU ISA
This patch deprecates HSA-based memory request types and adds new
types that can be used by real ISA instructions.

Change-Id: Ie107a69d8a35e9de0853f1407392ad01a8b3e930
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28408
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 20:00:13 +00:00
Gabe Black
18e435546c mem: Default the SE translating port proxy alloc method to NextPage.
This is what's used in 99% of cases, so it makes sense to make it the
default.

Change-Id: I51535b3387d1c1a0d1d89e77cfca10363388b472
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29399
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-09 10:02:26 +00:00
Bobby R. Bruce
b801b9ed04 misc: Merge hotfix v20.0.0.2 into develop
Change-Id: Ia0ed6bfb70e2ebcb22274569556d690e315702bd
2020-06-08 15:27:51 -07:00
Bobby R. Bruce
96fce47678 misc: Updated release notes and version number
Change-Id: Ib8583c23f47010222c08ff5aa9cffb842235c784
2020-06-08 15:21:35 -07:00
Matthew Poremba
bbb6a3fe8d mem-ruby: Allow MachineID to be unordered key
Define an std::hash function so that MachineID may be used as a key
type for unordered STL containers.

Change-Id: Ibc3bc78149c69683207d8967542fa6e8d545f75c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29652
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-08 16:39:21 +00:00
Giacomo Travaglini
7ce081d583 misc: Remove any reference to the ALPHA ISA
Change-Id: Ie761cd69ae0e8e632ca2b92e63a404e8804f0e6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30015
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-08 09:00:55 +00:00
seanzw
e30ef9911f mem-ruby: Fix Prefetcher to RubyPrefetcher in StateMachine.
After renaming Prefetcher to RubyPrefetcher, the slicc generator
should be updated to correctly initialize the prefetcher with
the controller.

Change-Id: Ia12a4640c35aaedd70a4a14e5a10793b060ba924
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29974
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-06-05 22:14:12 +00:00