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arch-gcn3: Implement instruction v_div_scale_f32

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Instruction v_div_scale_f32 was unimplemented, the
implementation was added by mimicking v_div_scale_f64.

Change-Id: I89cdfd02ab01b5936de0e9f6c41e7f3fc4f10ae1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29919
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Xianwei Zhang
2018-05-04 17:44:30 -04:00
committed by Anthony Gutierrez
parent f552ab85cb
commit fbcdf880ee
1 changed files with 34 additions and 2 deletions
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36
src/arch/gcn3/insts/instructions.cc
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@@ -28746,8 +28746,40 @@ namespace Gcn3ISA
void
Inst_VOP3__V_DIV_SCALE_F32::execute(GPUDynInstPtr gpuDynInst)
{
panicUnimplemented();
}
Wavefront *wf = gpuDynInst->wavefront();
ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
ConstVecOperandF32 src2(gpuDynInst, extData.SRC2);
ScalarOperandU64 vcc(gpuDynInst, instData.SDST);
VecOperandF32 vdst(gpuDynInst, instData.VDST);
src0.readSrc();
src1.readSrc();
src2.readSrc();
if (extData.NEG & 0x1) {
src0.negModifier();
}
if (extData.NEG & 0x2) {
src1.negModifier();
}
if (extData.NEG & 0x4) {
src2.negModifier();
}
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (wf->execMask(lane)) {
vdst[lane] = src0[lane];
vcc.setBit(lane, 0);
}
}
vcc.write();
vdst.write();
} // execute
// --- Inst_VOP3__V_DIV_SCALE_F64 class methods ---
Inst_VOP3__V_DIV_SCALE_F64::Inst_VOP3__V_DIV_SCALE_F64(
InFmt_VOP3_SDST_ENC *iFmt)