Commit Graph

2935 Commits

Author SHA1 Message Date
Daniel R. Carvalho
79bab1dc5d mem: Adopt a memory namespace for memories
Encapsulate every class inheriting from Abstract or Physical
memories, and the memory controller in a memory namespace.

Change-Id: I228f7e55efc395089e3616ae0a0a6325867bd782
Issued-on: https://gem5.atlassian.net/browse/GEM5-983
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47309
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-09 11:24:10 +00:00
Daniel R. Carvalho
5635b3aaa2 mem: Adopt the memory namespace in qos files
Encapsulate everything qos-related in the gem5::memory
namespace.

Change-Id: Ib906ddd6d76b9d4a56f2eb705efe6cd498829155
Issued-on: https://gem5.atlassian.net/browse/GEM5-983
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47308
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-09 11:24:10 +00:00
Davide Basilio Bartolini
86c3f08d13 base-stats: Fix stat descriptions
Change-Id: Ib43dc9261287f10c615786a0d533304ab55ac232
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47741
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-08 10:33:35 +00:00
Daniel R. Carvalho
5ff1fac819 misc: Rename Debug namespace as debug
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

gem5::Debug became gem5::debug.

Change-Id: Ic04606baab3317d2e58ab3ca9b37fc201c406ee8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47305
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 23:18:59 +00:00
Daniel R. Carvalho
60e4ad955d mem-ruby: Add a ruby namespace
Encapsulate all ruby-related files in a ruby namespace.

Change-Id: If642c9751ecefc35b45c5dd69d85e67813cc5224
Issued-on: https://gem5.atlassian.net/browse/GEM5-984
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47307
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 23:18:59 +00:00
Boris Shingarov
c046e61216 base: Dump page table over RSP
Add a non-standard extension to the RSP protocol: the "." command
requests a dump of the simulated page table.
The dump consists of concatenated records, one record per page table
entry.  Each record contains the entry's "virtual" value written as
hex, followed by a colon (:), followed by the entry's "physical" value
written as hex, followed by a semicolon (;).

At the time of writing, one practical use of this feature (in
combination with the "shared_backstore" parameter) is extremely fast
Miranda-Ingalls simulation of JIT compilers.

Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47719
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 22:54:27 +00:00
Hoa Nguyen
9a2efa07c5 scons: Explicitly add librt to scons
gem5 uses the `shm_open()` funciton from <sys/mman.h>.
This function requires linking to librt.

JIRA: https://gem5.atlassian.net/browse/GEM5-1015

Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47659
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 21:37:15 +00:00
Giacomo Travaglini
d1cdcb311b misc: Move Mode and Translation from BaseTLB to BaseMMU
This is a step towards moving most of the TLB logic to the
MMU class.

Change-Id: Id6b1fb30aa89960705f165f9738f5b50aa1e6bdb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46779
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 08:44:13 +00:00
Gabe Black
d58b4f004e misc: Remove typedef (struct|enum) Foo in cpp files.
In C, to refer to a type without a struct or enum tag on the type, you
need to typedef it like this:

typedef struct
{
} Foo;

Foo foo;

In C++, this is unnecessary:

struct Foo
{
};

Foo foo;

Remove all of the first form in C++ files and replace them with the
second form.

Change-Id: I37cc0d63b2777466dc6cc51eb5a3201de2e2cf43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46199
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 08:35:12 +00:00
Daniel R. Carvalho
4b2118ed4b misc: Remove sim/cur_tick dependency from sim/core.hh
Remove this unnecessary dependency. Fixed all incorrect
includes of sim/core.hh.

Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43592
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-06 09:59:11 +00:00
Daniel R. Carvalho
00cd307b13 mem-garnet: Add a garnet namespace
Add a namespace encapsulating all garnet files.

GarnetSyntheticTraffic, from
cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
has not been added to this namespace.

Change-Id: I5304ad3130100ba325e35e20883ee9286f51a75a
Issued-on: https://gem5.atlassian.net/browse/GEM5-987
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47306
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-01 19:08:24 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Daniel R. Carvalho
24041d6b77 mem-cache: Add Signature-Based Hit Predictor replacement policy
Add the SHiP Replacement Policy, as described in "SHiP: Signature-
based Hit Predictor for High Performance Caching", by Wu et al.

Instruction Sequence signatures have not been implemented.

Change-Id: I44f00d26eab4c96c9c5bc29740862a87356d30d1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38118
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
4a3e99fbcb mem-cache: Allow sending packet information to replacement policy
Some replacement policies can use information such as address or
PC to improve their re-reference prediction.

Change-Id: I412eee09efa2f3511ca1ece76fc2732509df4745
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
ef99dc8310 mem-cache: Use PacketPtr in tags's accessBlock
Pass the packet to the tags, so that the replacement policies
more execution information.

Change-Id: I201884a6d60e3299fc3c9befebbb2e8b64a007f0
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38116
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
2911839c22 mem-cache: Make WeightedLRU inherit from LRU
WeightedLRU adds occupancy information to LRU, so remove the
duplicated code.

Change-Id: Ifec19ea59fb411a5ed7a891e8957b1ab93cdbf05
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47399
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
041134e8d9 mem-cache: Change invalidate signature to not const
Allow the replacement policy to be modified when an entry is
invalidated.

Change-Id: I7f5086795dbb93a6fab2b4994c757d509d782d79
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38115
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2021-06-30 02:11:56 +00:00
Daniel R. Carvalho
3f040bab87 mem-cache: Add the DRRIP replacement policy
Instantiate the Dynamic Re-Reference Interval Prediction, as defined
in "High Performance Cache Replacement Using Re-Reference Interval
Prediction (RRIP)", by Jaleel et al.

Change-Id: Id1d354c01e63ae49739263647ff25e5665f60d8c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37898
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-30 02:11:56 +00:00
Daniel R. Carvalho
fd79a761ad mem-cache: Implement a dueling Replacement Policy
Implement a template dueling replacement policy which monitors
two replacement policies to decide and select the one that
provides the least amount of misses.

Change-Id: I6a6e96a9388cce8f8c8cd7b9c1dbe9f0554ccc64
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37897
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-30 02:11:56 +00:00
Daniel R. Carvalho
df5b191609 mem-cache: Creation of dueling classes
Table policies (i.e., replacement, compression, etc) behave
differently depending on the workload, and it is often desired
to be able to selectively switch between them. In this case
the relevant metadata for all the policies must be added to
all of the entries being analyzed.

In order to avoid having to monitor all table entries, a few
of these entries are selected to be sampled and estimate
overall behavior. These sampled entries belong each to a
single policy. Then, based on the predominance of these
samples, the winning policy is applied to the other sets
(followers).

As of now, in order to avoid having to iterate over a vector,
there is a limited number of dueling instances, but it may be
easily extended, if needed.

Based on Set Dueling, proposed in "Adaptive Insertion Policies
for High Performance Caching".

Change-Id: I692a3e5e0ad98581d68167ad7e6b45ab2f4c7b10
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37895
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-30 02:11:56 +00:00
Bobby R. Bruce
32b4a8cd36 mem: Fix use-after-free bug
mem_pkt was deleted (via `delete respQueue.front()`) then used in the
following if statement (at `mem_pkt->isDram()`). This patch fixes this
issue.

Issue-on: https://gem5.atlassian.net/browse/GEM5-1009
Change-Id: Iac3b9078ce5acbdd87a0737a2c98ad887459661f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47239
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 20:28:14 +00:00
Tom Rollet
3beeea0f40 mem-cache: Add MSHR debuging information
Add debug statment in MSHR and MSHRQueue class to track the
number of free MSHR each time a new one is allocated/deallocated.

Also track the allocation/deallocation of each MSHR target.

Change-Id: I2533e7660da1cde3052425f8db8852e59d463b42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47041
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 07:06:30 +00:00
Tom Rollet
15cba2ad1c mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from Named
With this change, when using a DPRINTF statment on a class inheriting
from the Queue or QueueEntry class, the name at the start of the log
line will be meaningful.

Currently affected classes:
    MSHRqueue
    MSHR
    MSHR::TargetList
    WriteQueue
    WriteQueueEntry

Change-Id: I4e5ac080fec572961f9f1d9f88429ed6e72d8994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 07:06:18 +00:00
Tom Rollet
37635f290d mem-cache: change Cache debug flag to MSHR in MSHR code
Change-Id: I97ba0d5426d51d913649dcabb6d1ca862e4d137a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47039
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 07:06:18 +00:00
Carlos Falquez
6d07200693 mem-ruby: Add (BUSY_BLKD,SnpOnceFwd) transition
Add (BUSY_BLKD,SnpOnceFwd) cache transition
to the Ruby CHI protocol.

Change-Id: I150880b26dee869b48cfd16fb661b9487527a8cd
Signed-off-by: Carlos Falquez <c.falquez@fz-juelich.de>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46901
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 02:13:54 +00:00
Daniel R. Carvalho
30e770e137 python,scons,mem-ruby: Tag origin of generated files
This will make it easier to backtrack and modify
such files when needed.

Change-Id: If09b6f848e607fb21a0acf2114ce0b9b0aa4751f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47301
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-28 20:25:07 +00:00
Daniel R. Carvalho
297fa863de mem: Move QoS' MemSinkInterface into gem5::qos
This class has been mistakenly added outside the
qos namespace.

Change-Id: I12c5dc7558a689c771761754e59d78a8010e422f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47300
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-28 20:25:07 +00:00
Daniel R. Carvalho
223b0b388e mem: Conclude deprecation of MemObject
This has been marked as deprecated a few versions ago,
so it is safe to conclude its deprecation process.

Change-Id: I20d37700c97264080a7b19cf0cf9ccf8a5b65c32
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47299
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-28 20:25:07 +00:00
Nathanael Premillieu
40cb501a2f mem: format address in hex in the memory controller debug trace
Before it was using the decimal format contrary to
everywhere else in gem5.
This was making it difficult to follow an address in the trace
once going to main memory.

Change-Id: Ia0e7d1624b593d8a21d5b3563893e2c0bcc8ed1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-24 07:37:35 +00:00
Daniel R. Carvalho
499a1cc7e8 base-stats,mem: Fix empty Stats::Info names
Sub-groups should not contain empty names. To make sure
that is the case, generate tokens even if the string is
empty.

Before the name 'group1..group2' would generate 2 tokens:
'group1' and 'group2'. As such, validateStatName would
not be able to detect it was an invalid name. With this
change three tokens will be generated: 'group1', '',
and 'group2'. The empty string will then trigger the
item->empty() check, which will successfully inform that
such stat name is not valid.

SLICC was breaking this rule with one of its stats by
creating a sub-group (inTransLatHist) whose parent had
an empty name, so it has been fixed.

Change-Id: Ica5ca684911374d59a0a809636594d048d755deb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43590
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-17 21:09:51 +00:00
Matthew Poremba
c493d2c4ad sim,mem-ruby: Handle interleaved device memory
Device memories are used for PCI devices which have their own pools of
backing store memory such as amdgpu device. The check for an address
being in device memory previously did not handle multiple interleaved
memory devices with the same address range. Therefore, the device memory
check would fail if the interleaving masks did not match. This updates
the method to iterate through all device memories that handle the
RequestorID and returns true if any of the device memories contain the
packet address.

Change-Id: I9339d39c1cb54a5b9075c4a122c118fe61dc6fdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46381
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-14 15:48:51 +00:00
sacak32
b0f534346a mem-cache: queued prefetcher bug fix
In queued prefetcher, addToQueue function doesn't behave
correctly where the element must be added to the end of queue.
I fixed this bug.

Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Signed-off-by: Burak Öçalan <byrakocalan99@gmail.com>
Reported-by: Burak Öçalan <byrakocalan99@gmail.com>
Tested-by: Burak Öçalan <byrakocalan99@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46759
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-12 08:21:04 +00:00
Matthew Poremba
ca12a8997d mem-ruby,sim: Add support for VGA ROM memory region
Checks if the address is in a shadowed region, and sends the request
to pio to be serviced by the device backing up that range.

Based on: https://gem5-review.googlesource.com/c/amd/gem5/+/23484

Change-Id: I4d5b46cccd6203523008b2e9545d55eb62130964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46159
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-11 17:10:32 +00:00
Gabriel Busnot
40715206f4 mem-ruby: Fix RubySystem::functionalRead with partial data
Some protocol other than CHI require the read-write and/or read-only and/or
backing-store controller's buffers to be checked if the system is busy.

More details in issue GEM5-1000

Change-Id: I0ad6385ad5a88fc158e68e4c63c540504b817ccb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46561
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-08 07:56:09 +00:00
Gabriel Busnot
9c2aac17b9 mem-ruby: Rename WriteMask::cmpMask to containsMask
Avoids confusion as the function tests for inclusions and not for equality.

Change-Id: I4cd10e08af46f69feed26afc2d6c7f809bc5192b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46560
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-08 07:56:09 +00:00
Gabriel Busnot
5a5fb03c77 mem-ruby: Fix wrong test in CHI functional reads
A bad write mask inclusion test in CHI cache functionalRead and CHI data message
functionalRead was causing clean data not to be read in some cases. The issue is
detailed in issue GEM5-1002.

Change-Id: I91254fa87636e8d22a8b2f27ad375f68f997932d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46559
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-08 07:56:09 +00:00
Arthur Perais
c01b9cd62b mem: Fix bandwidth-delay calculation in AMPM prefetcher
The AMPM paper (https://www.jilp.org/vol13/v13paper3.pdf) defines
the bandwidth-delay calculation as :

  Mbandwidth= (Nrequests/Tepoch)×Tlatency

In the code, Tepoch and Tlatency are in ticks (which is okay),
but Tepoch is converted from Cycles (256K) to Ticks using the
clockEdge(Cycle c) function, which is incorrect as it yields currentTick
+ c * clockPeriod() instead of just c * clockPeriod().
In other words, the divider keeps increasing as time advances.

This patch substitutes clockEdge() with cyclesToTicks() to keep
the epoch length (Tepoch) constant throughout simulation.

Change-Id: I69dee29892fa4b9eb8de8715fd72a535e122687f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46479
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-05 16:24:41 +00:00
Daniel R. Carvalho
31de35c8be mem-ruby: Appease compiler with return values
Add default values for the cases where gem5 panics to
appease the compiler.

Change-Id: Ib15a63abfb6f1ffed6ce628f52a57388d2173c44
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46320
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-04 20:36:22 +00:00
Arthur Perais
efc9a68620 mem: Fix Best Offset Prefetcher (BOP) learning phase code.
According to the DPC paper : "If the best score is less
than or equal to a fixed value BADSCORE, we turn prefetchoff
during the next phase"

However, the current code will turn prefetch off if the best
*offset* of the learning phase is less than BADSCORE, which
is incorrect.

Change-Id: Ib5790fe1341f2dd6328ec3b018bc52012e376723
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46259
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-01 19:36:20 +00:00
Daniel R. Carvalho
93e5734685 mem: Rename "memory" variables as "mem"
Pave the way to a "memory" namespace by renaming all
the variables that have a naming conflict.

Change-Id: I8327256ed88f1791225fe158f023132850303472
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45438
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
98ac080ec4 base-stats,misc: Rename Stats namespace as statistics
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Stats became ::statistics.

"statistics" was chosen over "stats" to avoid generating
conflicts with the already existing variables (there are
way too many "stats" in the codebase), which would make
this patch even more disturbing for the users.

Change-Id: If877b12d7dac356f86e3b3d941bf7558a4fd8719
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45421
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
9f55bb8478 base: Rename Loader namespace as loader
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Loader became ::loader.

Change-Id: Ifddf11ab4d5d7358032fbc523bc923c0a9feedbd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45424
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
a658ea043f base,dev,mem-ruby: Rename m5 namespace as gem5
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::m5 became ::gem5.

Change-Id: I250b4354113fcd6005dc4144ae378552cb8f6717
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45437
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
4dd099ba3d misc: Rename Enums namespace as enums
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Enums became ::enums.

Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
90aab2f926 sim: Rename ProbePoints namespace as probing
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ProbePoints became ::probing.

"probing" was chosen over "probe_points" because the
namespace contains more than solely probe points; it
contains all classes related to the act of probing.

Change-Id: I44567974a521707593739a2bd5933391803e5b51
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45412
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
e291376f07 cpu,mem: Rename ContextSwitchTaskId namespace
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ContextSwitchTaskId becomes ::context_switch_task_id.

Change-Id: If3884a5da7afe6144954d556b3b54f659bb7afb5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45411
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
df72e9d548 mem-cache: Rename Prefetcher namespace as prefetch
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Prefetcher became ::prefetcher.

"prefetch" was chosen over "prefetcher" to avoid generating
conflicts with the already existing variables. "prefetcher"
is a name that is expected to be more common in user's code
than "prefetch".

Change-Id: I8f07217f278a0229e05545b7847f2620ed208c66
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45410
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Gabe Black
a91af24e60 misc: Clean up ISA switching header includes.
Remove includes that aren't needed, including ones for
config/the_isa.hh.

Also stop using switching includes when the ISA is known.

Change-Id: I2af6c88dcaf511b086ec808b0ba3196179982af2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40336
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-28 23:41:03 +00:00
Daniel R. Carvalho
2a0e4ae3ea mem-cache: Rename Encoder namespace as encoder
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

compression::Encoder became compression::encoder.

Change-Id: I3ff2693fbbfc366952cf0f03414a00debae27635
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45408
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-28 23:01:26 +00:00
Daniel R. Carvalho
c84888b67a mem-cache: Rename encoder variables as indexEncoder
Pave the way for an encoder namespace.

Change-Id: I5b55ac18a2973e25e53b097cd407861f5f60d646
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45407
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-28 23:01:26 +00:00